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Volumn 7, Issue 2, 2010, Pages

Applied inference: Case studies in microarchitectural design

Author keywords

Microarchitecture; Regression; Simulation; Statistics

Indexed keywords

CLUSTERING HEURISTICS; COMPREHENSIVE DESIGNS; CORE DESIGN; DESIGN COMPLEXITY; DESIGN EVALUATION; DESIGN SPACE EXPLORATION; EFFICIENT DESIGNS; HETEROGENEOUS MULTICORE; LARGE DESIGNS; MICRO ARCHITECTURES; MICROARCHITECTURAL SIMULATION; OPTIMAL ARCHITECTURE; PARETO FRONTIERS; PARETO-OPTIMAL DESIGN; PIPELINE DEPTH; POWER BUDGETS; REGRESSION; REGRESSION MODEL; SHARED RESOURCES; SIMULATION; SIMULATION PARADIGM; SPATIAL SAMPLING; STATISTICAL INFERENCE; UPPER BOUND;

EID: 77958078100     PISSN: 15443566     EISSN: 15443973     Source Type: Journal    
DOI: 10.1145/1839667.1839670     Document Type: Article
Times cited : (14)

References (50)
  • 4
    • 0346898058 scopus 로고    scopus 로고
    • New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors
    • BROOKS, D., BOSE, P., SRINIVASAN, V., GSCHWIND, M., EMMA, P., AND ROSENFIELD, M. 2003. New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors. IBM J. Res. Dev. 47, 5/6, 653-670.
    • (2003) IBM J. Res. Dev. , vol.47 , Issue.5-6 , pp. 653-670
    • Brooks, D.1    Bose, P.2    Srinivasan, V.3    Gschwind, M.4    Emma, P.5    Rosenfield, M.6
  • 9
    • 1442333868 scopus 로고    scopus 로고
    • Quantifying the impact of input data sets on program behavior and its applications
    • EECKHOUT, L. AND H. VANDIERENDONCK, K. D. 2003. Quantifying the impact of input data sets on program behavior and its applications. J. Instruction-Level Parall. 5.
    • (2003) J. Instruction-Level Parall. , vol.5
    • Eeckhout, L.H.1    Vandierendonck, K.D.2
  • 10
    • 0242577987 scopus 로고    scopus 로고
    • Statistical simulation: Adding efficiency to the computer designer's toolbox
    • EECKHOUT, L.,NUSSBAUM, S., SMITH, J., AND DEBOSSCHERE, K. 2003. Statistical simulation: Adding efficiency to the computer designer's toolbox. IEEE Micro 23, 5, 26-38.
    • (2003) IEEE Micro 23 , vol.5 , pp. 26-38
    • Eeckhout, L.1    Nussbaum, S.2    Smith, J.3    Debosschere, K.4
  • 12
    • 67650312346 scopus 로고    scopus 로고
    • A mechanistic performance modeling for studying resource scaling in out-of-order processors
    • EYERMAN, S., EECKHOUT, L., KARKHANIS, T., AND SMITH, J. 2009. A mechanistic performance modeling for studying resource scaling in out-of-order processors. ACM Trans. Comput. Syst. 27, 2, 1-37.
    • (2009) ACM Trans. Comput. Syst. , vol.27 , Issue.2 , pp. 1-37
    • Eyerman, S.1    Eeckhout, L.2    Karkhanis, T.3    Smith, J.4
  • 23
    • 35348870650 scopus 로고    scopus 로고
    • Automated design of application specific superscalar processors: An analytical approach
    • ACM, New York
    • KARKHANIS, T. AND SMITH, J. 2007. Automated design of application specific superscalar processors: An analytical approach. In Proceedings of the 34st Annual Symposium on Computer Architecture. ACM, New York, 402-411.
    • (2007) Proceedings of the 34st Annual Symposium on Computer Architecture , pp. 402-411
    • Karkhanis, T.1    Smith, J.2
  • 24
    • 20344374162 scopus 로고    scopus 로고
    • Niagara: A 32-way multithreaded sparc processor
    • KONGETIRA, P., AINGARAN, K., AND OLUKOTUN, K. 2005. Niagara: A 32-way multithreaded sparc processor. IEEE Micro 25, 2, 21-29.
    • (2005) IEEE Micro 25 , vol.2 , pp. 21-29
    • Kongetira, P.1    Aingaran, K.2    Olukotun, K.3
  • 30
    • 57749176188 scopus 로고    scopus 로고
    • Roughness of microarchitectural design topologies and its implications for optimization
    • IEEE, Los Alamitos, CA
    • LEE, B. AND BROOKS, D. 2008b. Roughness of microarchitectural design topologies and its implications for optimization. In Proceedings of the 14th Symposium on High-Performance Computer Architecture. IEEE, Los Alamitos, CA, 240-251.
    • (2008) Proceedings of the 14th Symposium on High-Performance Computer Architecture , pp. 240-251
    • Lee, B.1    Brooks, D.2
  • 36
    • 0032683935 scopus 로고    scopus 로고
    • Environment for PowerPC microarchitecture exploration
    • MOUDGILL, M.,WELLMAN, J., AND MORENO, J. 1999. Environment for PowerPC microarchitecture exploration. IEEE Micro 19, 3, 9-14.
    • (1999) IEEE Micro 19 , vol.3 , pp. 9-14
    • Moudgill, M.1    Wellman, J.2    Moreno, J.3
  • 47
    • 28244457802 scopus 로고    scopus 로고
    • Improving computer architecture simulationmethodology by adding statistical rigor
    • YI, J.,LILJA, D., AND HAWKINS, D. 2005. Improving computer architecture simulationmethodology by adding statistical rigor. IEEE Comput. 54, 11, 1360-1373.
    • (2005) IEEE Comput. , vol.54 , Issue.11 , pp. 1360-1373
    • Yi, J.1    Lilja, D.2    Hawkins, D.3
  • 49
    • 0035273395 scopus 로고    scopus 로고
    • Inherently lower-power high-performance superscalar architectures
    • ZYUBAN, V. AND KOGGE, P. 2001. Inherently lower-power high-performance superscalar architectures. IEEE Trans. Comput. 50, 3, 268-285.
    • (2001) IEEE Trans. Comput. , vol.50 , Issue.3 , pp. 268-285
    • Zyuban, V.1    Kogge, P.2
  • 50
    • 0348017034 scopus 로고    scopus 로고
    • Balancing hardware intensity inmicroprocessor pipelines
    • ZYUBAN, V. AND STRENSKI, P. 2003. Balancing hardware intensity inmicroprocessor pipelines. IBM J. Res. Dev. 47, 5/6, 585-598.
    • (2003) IBM J. Res. Dev. , vol.47 , Issue.5-6 , pp. 585-598
    • Zyuban, V.1    Strenski, P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.