Small-defect detection in sub-100nm SRAM cells using a WL-pulse timing-margin measurement scheme

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2010, Pages 37-38

  Morita, Yasuhiro ^a   Nose, Koichi ^a   Noguchi, Koichiro ^a   Takami, Shinya ^b   Goto, Kenji ^b   Aimoto, Yoshiharu ^b   Kimura, Akira ^b   Mizuno, Masayuki ^a  

^a NEC CORPORATION   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

Small defect; SRAM test; WL pulse timing margin

Indexed keywords

AREA OVERHEAD; CONVENTIONAL TESTING; DEFECT DETECTION; DELAY DEFECTS; DELAY VARIATION; HIGH RESOLUTION; PERIPHERAL CIRCUITRY; PULSE TIMING; SMALL DEFECT; SRAM CELL; SRAM TEST; STATISTICAL ANALYSIS; SUB-100 NM; WIDTH CONTROL;

DEFECTS; ELECTRON DEVICE TESTING; SENSITIVITY ANALYSIS; STATIC RANDOM ACCESS STORAGE; TIME MEASUREMENT;

VLSI CIRCUITS;

EID: 77958004007     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2010.5560264     Document Type: Conference Paper

References (7)

1. A. Pavlov, et al., IEEE ITC, pp.816-825, Nov. 2005.
2. K. Kang, et al., DAC, pp.358-363, June 2007.
3. C.J. Brennan, et al., CICC, pp.345-348, Oct. 2004.
4. Q. Chen, et al., IEEE VLSI Test Symp., pp.292-297, May 2005.
5. B. Arkin, et al., ISSCC, pp.348-349, Feb. 2004.
6. A. Shibayama, et al., Symp. VLSI Circ., pp.158-159, June 2007.
7. T. Okayasu, et al., ISSCC, pp.426-427, Feb. 2006.