A 5.5-mW +9.4-dBm IIP3 1.8-dB NF CMOS LNA employing multiple gated transistors with capacitance desensitization

IEEE Transactions on Microwave Theory and Techniques

Volumn 58, Issue 10, 2010, Pages 2529-2537

  Jin, Tae Hwan ^a   Kim, Tae Wook ^a  

^a Yonsei University   (South Korea)

Author keywords

Harmonic feedback; linearity; low noise amplifier (LNA); multiple gated transistors (MGTRs); third order intercept point (IIP3)

Indexed keywords

CMOS LNA; CMOS TECHNOLOGY; DE-SENSITIZATION TECHNIQUES; HARMONIC FEEDBACK; INPUT MATCHING NETWORKS; LINEARITY; MULTIPLE GATED TRANSISTORS (MGTRS); NOISE CONTRIBUTIONS; QUALITY FACTORS; SECOND ORDERS; SECOND-ORDER DISTORTION; SOURCE DEGENERATION; SOURCE NODES; THIRD ORDER INTERMODULATION DISTORTION; THIRD-ORDER INTERCEPT POINT;

CAPACITANCE; CMOS INTEGRATED CIRCUITS; CODE DIVISION MULTIPLE ACCESS; HARMONIC ANALYSIS; HIGH ELECTRON MOBILITY TRANSISTORS; LINEARIZATION; MICROSTRIP DEVICES; NOISE FIGURE; TRANSISTORS;

LOW NOISE AMPLIFIERS;

EID: 77957992276     PISSN: 00189480     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMTT.2010.2063790     Document Type: Article

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