Analysis of dynamic voltage scaling for system level energy management

Workshop on Power Aware Computing and Systems, HotPower 2008

Volumn , Issue , 2008, Pages

  Dhiman, Gaurav ^a   Pusukuri, Kishore Kumar ^b   Rosing, Tajana ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY CONSERVATION; VOLTAGE SCALING;

COMPUTING SYSTEM; CPU ARCHITECTURE; CPU-INTENSIVE; LIMITED ENERGIES; LOW POWER STATE; MEMORY SUBSYSTEMS; STATE-OF-THE-ART SYSTEM; SYSTEM LEVELS;

MEMORY ARCHITECTURE;

EID: 77957951795     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. http://www.intel.com/support/processors/xeon/sb/cs012641.htm.
2. M. Weiser, B. Welch, A. Demers, and S. Shenker, “Scheduling for reduced cpu energy,” in OSDI, 1994, p. 2.
3. A. Varma, B. Ganesh, M. Sen, S. R. Choudhury, L. Srinivasan, and J. Bruce, “A control-theoretic approach to dynamic voltage scheduling,” in CASES, 2003, pp. 255-266.
4. G. Quan and X. Hu, “Minimum energy fixed-priority scheduling for variable voltage processor,” in DATE'02, 2002, p. 782.
5. Y. Zhu and F. Mueller, “Feedback edf scheduling of real-time tasks exploiting dynamic voltage scaling,” Real-Time Syst., vol. 31, no. 1-3, pp. 33-63, 2005.
6. D. Shin, J. Kim, and S. Lee, “Low-energy intra-task voltage scheduling using static timing analysis,” in DAC'01, 2001, pp. 438-443.
7. A. Azevedo, I. Issenin, R. Cornea, R. Gupta, N. Dutt, A. Veidenbaum, and A. Nicolau, “Profile-based dynamic voltage scheduling using program checkpoints,” in DATE '02, 2002, p. 168.
8. C. Isci, G. Contreras, and M. Martonosi, “Live, runtime phase monitoring and prediction on real systems with application to dynamic power management,” in MICRO, 2006, pp. 359-370.
9. G. Dhiman and T. S. Rosing, “Dynamic voltage frequency scaling for multi-tasking systems using online learning,” in ISLPED, 2007, pp. 207-212.
10. S. Bird, A. Phansalkar, L. K. John, A. Mericas, and R. Indukuru, “Characterization of performance of spec cpu benchmarks on intel's core microarchitecture based processor,” SPEC Benchmark Workshop, 2007.
11. http://www.intel.com/technology/architecturesilicon/intel64/45nm core2 whitepaper.pdf.