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Volumn , Issue , 2003, Pages 121-128

An analysis of determinacy using a trace-theoretic model of asynchronous circuits

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; SEMANTICS;

EID: 77957933195     PISSN: 26431394     EISSN: 26431483     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.2003.1199172     Document Type: Conference Paper
Times cited : (7)

References (17)
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    • Huffman, D.A.1
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    • Josephs, M.B.1
  • 6
    • 2542561229 scopus 로고    scopus 로고
    • The use of si-algebra in the design of sequencer circuits
    • M.B. Josephs, A.M. Bailey, The Use of Si-Algebra in the Design of Sequencer Circuits, Formal Aspects of Computing, 9:395-408, 1997.
    • (1997) Formal Aspects of Computing , vol.9 , pp. 395-408
    • Josephs, M.B.1    Bailey, A.M.2
  • 7
    • 0000087207 scopus 로고
    • The semantics of a simple language for parallel programming
    • J.L. Rosenfeld (ed.) North-Holland
    • G. Kahn, The semantics of a simple language for parallel programming, in J.L. Rosenfeld (ed.) Information Processing '74, North-Holland, 1974, pp. 471-475.
    • (1974) Information Processing '74 , pp. 471-475
    • Kahn, G.1
  • 8
    • 84978982527 scopus 로고
    • A fundamental theorem of asynchronous parallel computation
    • R.M. Keller, A fundamental theorem of asynchronous parallel computation, Lect. Notes in Comp. Sci., 24:102-112, 1975.
    • (1975) Lect. Notes in Comp. Sci. , vol.24 , pp. 102-112
    • Keller, R.M.1
  • 9
    • 0002927123 scopus 로고
    • Programming in VLSI: From commmunicating processes to delay-insensitive circuits
    • C.A.R. Hoare (ed.) Addison-Wesley
    • A.J. Martin, Programming in VLSI: From Commmunicating Processes to Delay-Insensitive Circuits, in C.A.R. Hoare (ed.) UT Year of Programming: Institute on Concurrent Programming, pp. 1-64, Addison-Wesley, 1989.
    • (1989) UT Year of Programming: Institute on Concurrent Programming , pp. 1-64
    • Martin, A.J.1
  • 12
    • 0001951703 scopus 로고
    • System timing
    • Chapter 7 in C. Mead, L. Conway (eds.) Addison-Wesley
    • C.L. Seitz, System Timing, Chapter 7 in C. Mead, L. Conway (eds.) Introduction to VLSI Systems, Addison-Wesley, 1980, pp. 218-262.
    • (1980) Introduction to VLSI Systems , pp. 218-262
    • Seitz, C.L.1
  • 13
    • 0029407843 scopus 로고
    • Correct compilation of specifications of deterministic asynchronous circuits
    • S.F. Scott, A.E. Zwarico, Correct Compilation of Specifications of Deterministic Asynchronous Circuits, Formal Methods in System Design, 7:155-226, 1995.
    • (1995) Formal Methods in System Design , vol.7 , pp. 155-226
    • Scott, S.F.1    Zwarico, A.E.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.