Sub-10 μa reset in NiO-based resistive switching memory (RRAM) cells

2010 IEEE International Memory Workshop, IMW 2010

Volumn , Issue , 2010, Pages

  Nardi, F ^a   Ielmini, D ^a   Cagli, C ^a   Spiga, S ^b   Fanciulli, M ^b   Goux, L ^c   Wouters, D J ^c  

^a POLITECNICO DI MILANO   (Italy)

^b LABORATORIO MDM   (Italy)

^c IMEC   (Belgium)

Author keywords

Crossbar architecture; Nonvolatile memory; Resistive switching memory (RRAM); Transition metal oxide

Indexed keywords

ARRAY STRUCTURES; CROSS-BAR MEMORIES; CROSSBAR ARCHITECTURE; HIGH CURRENTS; HIGH DENSITY MEMORY; HIGH-DENSITY; INTEGRATED SERIES; MOS-FET; NON-VOLATILE MEMORIES; RESET CURRENTS; RESISTIVE SWITCHING MEMORIES; TRANSITION METAL OXIDE;

SWITCHING; SWITCHING SYSTEMS; TRANSITION METAL COMPOUNDS; TRANSITION METALS;

NONVOLATILE STORAGE;

EID: 77957916658     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMW.2010.5488317     Document Type: Conference Paper

References (15)

1. R. Waser and M. Aono, "Nanoionics-based resistive switching memories," Nature Mater., vol. 6, pp. 833-840, 2007.
2. I. Baek, et al, "Highly scalable nonvolatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses," in IEDM Tech. Dig., 2004, pp. 587-590.
3. x thin-film diodes for cross-point memory applications," Adv. Mater. 20, 3066-3069, 2008.
4. Y. Sato, et al, "Sub-100-μA reset current of nickel oxide resistive memory through control of filamentary conductance by current limit of MOSFET," IEEE Trans. Electron Devices, vol. 55, pp. 1185-1191, 2008.
5. x brought about by reducing a parasitic capacitance," Appl. Phys. Lett., vol. 93, p. 033506, 2008.
6. S. Spiga, et al, "Resistance switching in amorphous and crystalline binary oxides grown by electron beam evaporation and atomic layer deposition," Microelectron. Eng., vol. 85, pp. 2414-2419, 2008.
7. D. Ielmini, C. Cagli, and F. Nardi, "Resistance transition in metal oxides induced by electronic threshold switching," Appl. Phys. Lett., vol. 94, p. 063511, 2009.
8. T.-N. Fang, et al, "Erase mechanism for copper oxide resistive switching memory cells with nickel electrode," in IEDM Tech. Dig., 2006, pp. 789-792.
9. K. Tsunoda, et al, "Low power and high speed switching of Ti-doped NiO ReRAM under the unipolar voltage source of less than 3 V," in IEDM Tech. Dig., 2007, pp. 767 - 770.
10. 2 based RRAM," in IEDM Tech. Dig., 2008, pp. 297-300.
11. D. Ielmini, F. Nardi, A. Vigani, E. Cianci, and S. Spiga, "Read-disturb limited reliability of multilevel NiO-based resistive-switching memory," as discussed at 2009 IEEE SISC, Arlington, VA, Dec. 3-5, 2009.
12. J. H. Oh, et al, "Full Integration of Highly Manufacturable 512Mb PRAM Based on 90nm Technology," in IEDM Tech. Dig., 2006, pp. 49-52.
13. 2 cell size driven by low-contact-resistivity poly-Si diode," Symp. VLSI Tech. Dig. 24, 2009, pp. 24-25.
14. M.-J. Lee et al., "2-stack 1D-1R cross-point structure with oxide diodes as switch elements for high density resistance RAM application," in IEDM Tech. Dig., 2007, pp. 771-774.
15. G. Tallarida, et al, "Low temperature rectifying junctions for crossbar non-volatile memory devices," in IEEE IMW Tech. Dig., 2009.