Key sub 1nm EOT CMOS enabler by comprehensive PMOS design

Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010

Volumn , Issue , 2010, Pages 116-117

  Tseng, J ^b   Ragnarsson, L A ^a   Schram, T ^a   Akheyar, A ^c   Okuno, Y ^d   Li, Z L ^a   Aoulaiche, M ^a   Rohr, E ^a   Witters, T ^a   Adelmann, C ^a   Delabie, A ^a   Paraschiv, V ^a   Kerner, C ^a   Xiong, K ^e   Mueller, M ^e   Hoffmann, T ^a   Absil, P ^a   Biesemans, S ^a  

^a IMEC   (Belgium)

^b TSMC   (Belgium)

^c INFINEON TECHNOLOGIES AG   (Germany)

^d Panasonic   (Belgium)

^e NXP TSMC Research Center   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

COMPREHENSIVE STUDIES; DRIVE CURRENTS; GATE-LAST; HIGH-PERFORMANCE CMOS; LIFE-TIMES; NOVEL PROCESS;

EID: 77957911098     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2010.5488923     Document Type: Conference Paper

References (5)

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3. J. Huang et al., Symp. VLSI Dig., p 34 (2009);
4. J. Robertson et al., Appl. Phys. Letter. 91, p.132912 (2007);
5. S. Kubicek et al., VLSI, p. 130 (2008)