Investigations of Cu bond structures and demonstration of a wafer-level 3D integration scheme with W TSVs

Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010

Volumn , Issue , 2010, Pages 162-163

  Chen, K N ^a   Cabral Jr , C ^b   Lee, S H ^c   Andry, P S ^b   Lu, J Q ^d  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c LABORATORY FOR PHYSICAL SCIENCES   (United States)

^d RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

3D; Cu bonding; Oxide recess and lock n key

Indexed keywords

3D; BOND STRUCTURES; CU BONDINGS; ELECTRICAL CHARACTERISTIC; VIA CHAIN; WAFER-LEVEL 3D INTEGRATION; WAFER-LEVEL THREE-DIMENSIONAL (3D) INTEGRATION;

THREE DIMENSIONAL; WAFER BONDING;

KEYS (FOR LOCKS);

EID: 77957904465     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2010.5488904     Document Type: Conference Paper

References (3)

1. P. Morrow et al, Proceedings of AMC, Oct 2004.
2. K.N. Chen et al, Digest of IEDM, Dec 2006.
3. F. Liu et al, Digest of IEDM, Dec 2008.