3D integration technology for energy efficient system design

Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010

Volumn , Issue , 2010, Pages 100-103

  Borkar, Shekhar ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; CMOS SCALING; COMPLEX SYSTEMS; ENERGY EFFICIENT; ENERGY EFFICIENT SYSTEMS; INTEGRATION CAPACITY; NEW TECHNOLOGIES;

THREE DIMENSIONAL;

TECHNOLOGY;

EID: 77957904253     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2010.5488932     Document Type: Conference Paper

References (5)

1. Koyanagi et al., Future System-on-Silicon LSI Chips, IEEE Micro, July/August 1998
2. J. Barth, et al, A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier, ISSCC 2007.
3. S. Vangal et al, An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS, JSSC, Jan 2008
4. Y. Hoskote et al, Teraflop Prototype Processor with 80 Cores, Hot Chips conference, 2007
5. Y. Hoskote et al, A 5-GHz Mesh Interconnect for a Teraflops Processor, IEEE Micro, Sep-Oct 2007