A new asynchronous parallel global optimization method based on simulated annealing and differential evolution

Applied Soft Computing Journal

Volumn 11, Issue 1, 2011, Pages 1481-1489

  Olenšek, Jernej ^a   Tuma, Tadej ^a   Puhan, Janez ^a   Brmen, Árpád ^a  

^a UNIVERSITY OF LJUBLJANA   (Slovenia)

Author keywords

Analog integrated circuit design; Differential evolution; Parallel global optimization; Simulated annealing

Indexed keywords

ANALOG IC DESIGN; ANALOG INTEGRATED CIRCUIT; ANALOG INTEGRATED CIRCUIT DESIGN; ANALYTICAL TESTS; ASYNCHRONOUS PARALLEL; AUTOMATED DEVICE; COOLING SCHEDULE; DEVICE SIZING; DIFFERENTIAL EVOLUTION; FINE TUNING; GLOBAL OPTIMIZATION METHOD; LOCAL SEARCH; MASTER-SLAVE; OPTIMAL CIRCUIT; PARALLEL EFFICIENCY; PARALLEL GLOBAL OPTIMIZATION; PARALLEL SYSTEM; SAMPLING EFFICIENCY; SIMULATED ANNEALING ALGORITHMS;

ANNEALING; BIOLOGY; DESIGN; EVOLUTIONARY ALGORITHMS; FEATURE EXTRACTION; GLOBAL OPTIMIZATION; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; LINEAR INTEGRATED CIRCUITS;

SIMULATED ANNEALING;

EID: 77957897297     PISSN: 15684946     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.asoc.2010.04.019     Document Type: Article

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