Wafer-on-wafer (WOW) stacking with damascene-contact TSV for 3D integration

Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010

Volumn , Issue , 2010, Pages 158-159

  Maeda, Nobuhide ^a   Kitada, Hideki ^a   Fujimoto, Koji ^b   Suzuki, Kousuke ^b   Nakamura, Tomoji ^c   Kawai, Akihito ^d   Arai, Kazuhisa ^d   Ohba, Takayuki ^a  

^a UNIVERSITY OF TOKYO   (Japan)

^b DAI NIPPON PRINTING CO LTD   (Japan)

^c FUJITSU LABORATORIES LTD   (Japan)

^d DISCO CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; ADHESIVE LAYERS; DAMASCENE TECHNIQUE; ELECTRICAL FAILURES; ON-WAFER; PLANARIZING; THROUGH-SILICON VIA; VOID FORMATION; WAFER BONDING PROCESS; WAFER STACKING;

SILICON WAFERS;

WAFER BONDING;

EID: 77957894220     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2010.5488906     Document Type: Conference Paper

References (4)

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3. N. Maeda, et al, Proc. AMC2008 (2008) 91
4. R. Labie, et al, Proc. IITC2008 (2008) 19