FDSOI CMOS with dielectrically-isolated back gates and 30nm LG high-κ/metal gate

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2010, Pages 43-44

  Khater, M ^a   Cai, J ^a   Dennard, R H ^a   Yau, J ^a   Wang, C ^a   Shi, L ^a   Guillorn, M ^a   Ott, J ^a   Ouyang, Q ^a   Haensch, W ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BACK GATES; CMOS DEVICES; FULLY DEPLETED; GATE LENGTH; ISOLATION STRUCTURES; METAL GATE; PERFORMANCE TOLERANCES; POWER GATINGS; SHALLOW TRENCH ISOLATION; SOI CMOS; SYSTEMATIC PROCESS;

CMOS INTEGRATED CIRCUITS;

POLYSILICON;

EID: 77957861098     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2010.5556125     Document Type: Conference Paper

References (5)

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3. R. Tsuchiya et al, IEDM, p. 631 (2004).
4. J. Yau et al, VLSI-TSA, p. 84 (2009).
5. C. Fenouillet-Beranger, et al, IEDM, p. 667 (2009).