Enabling application-specific integrated circuits on limited pattern constructs

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2010, Pages 139-140

  Morris, Daniel ^a   Rovner, Vyacheslav ^a   Pileggi, Larry ^a   Strojwas, Andrzej ^a   Vaidyanathan, Kaushik ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CO-OPTIMIZATION; COMPLEX DESIGNS; HOT SPOT; LEVEL DENSITY; MEMORY BLOCKS;

DESIGN; INTEGRATED CIRCUITS;

VLSI CIRCUITS;

EID: 77957859951     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2010.5556202     Document Type: Conference Paper

References (3)

1. T. Jhaveri, U. Urslan, V. Rovner, L. Pileggi & A.J. Strojwas, Application of the Cost-Per-Good-Die Metric for Process-Design Co-optimization, SPIE Advanced Lithography Conference, Selected for Keynote Presentation, Feb. 2010.
2. M. Fritze, et. al., "Hybrid Optical Maskless Lithography: Scaling Beyond the 45nm Node." J. Vac. Sci. Tech. B, 2005.
3. T. Jhaveri, et. al., Design Technology Co-optimization for Predictive Technology Scaling Beyond Gratings, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 4, April 2010.