Optimization of shallow and deep trench isolation structures for ultra-high-speed bipolar LSIs

Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting

Volumn 1992-October, Issue , 1992, Pages 104-107

  Itoh, N ^a   Yoshino, C ^a   Matsuda, S ^a   Tsuboi, Y ^a   Inou, K ^a   Katsumata, Y ^a   Iwai, H ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

TEMPERATURE;

DEEP TRENCH ISOLATION; LOW-TEMPERATURE DEPOSITION; PROCESS SIMPLIFICATION; RESIDUAL MECHANICAL STRESS; ULTRA HIGH SPEED;

LSI CIRCUITS;

EID: 77956975026     PISSN: 10889299     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/BIPOL.1992.274073     Document Type: Conference Paper

References (3)

1. Y. Katsumata, I. Katakabe, N. Itoh, E. Tsukioka, C. Yoshino, and H. Iwai, "Stress analysis around trench isolation for bipolar LSIs," BCTM, p.271, 1991.
2. C. T. Chung, and P. E. Lu, "On the scaling property of trench isolation capacitance for advanced high-performance ECL circuit," IEDM, p.799, 1989.
3. V. F. Drobny, T. Yamaguchi, C. Hachen, S. Dotarrar, A. Tang, and Y. C. S. Yu, "Planalized self-aligned double-polysilicon bipolar technology," BCTM, p.115, 1988.