Charge Injection in Analog MOS Switches

IEEE Journal of Solid-State Circuits

Volumn 22, Issue 6, 1987, Pages 1091-1097

  Wegmann, George ^a   Yittoz, Eric A ^b   Rahali, Fouad ^a  

^a EPFL   (Switzerland)

^b CSEM   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 77956929068     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.1987.1052859     Document Type: Article

References (19)

1. E. Suarez, P. R. Gray, and D. A. Hodges, “All-MOS charge redistribution analog-to-digital conversion techniques,” IEEE J. Solid-State Circuits, vol. SC-10, pp. 379–385, Dec. 1975.
2. E. A. Vittoz, “Microwatt switched capacitor circuit design,” Electrocomp. Sci. Technol., vol. 9, pp. 263–273, 1982.
3. E. Vittoz, “Dynamic analog techniques,” in Design of MOS VLSI Circuits for Telecommunications, Y. Tsividis and P. Antognetti, Eds. Englewood Cliffs, NJ: Prentice-Hall, 1985.
4. E. A. Vittoz, “Design of high-performance analog circuits on digital CMOS chips,” IEEE J. Solid-State Circuits, vol. SC-20, no. 3, pp. 657–665, June 1985.
5. B. J. Sheu and C. M. Hu, “Switched induced error voltage on a switched capacitor,” IEEE J. Solid-State Circuits, vol. SC-19, no. 4, pp. 519–525, Aug. 1984.
6. J. H. Shieh, M. Patil, and B. J. Sheu, “Modeling charge injection in MOS analog switches,” IEEE Trans. Circuits Syst., vol. CAS-34, pp. 214–216, Feb. 1987.
7. B. J. Sheu, J. H. Shieh, and M. Patil, “Measurement and analysis of charge injection in MOS analog switches,” IEEE J. Solid-State Circuits, vol. SC-22, no. 2, pp. 277–281, Apr. 1987.
8. W. B. Wilson, H. Z. Massoud, E. J. Swanson, R. T. George, and R. B. Fair, “Measurement and modeling of charge feedthrough in n-channel MOS analog switches,” IEEE J. Solid-State Circuits, vol. no. Dec. 1985.
9. C. Turchetti, P. Mancini, and G. Masetti, “A CAD-oriented non-quasi-static approach for the transient analysis of MOS IC's,” IEEE J. Solid-State Circuits, vol. SG-21, no. 5, pp. 827–836, Oct. 1986.
10. J. B. Kuo, R. W. Dutton, and B. A. Wooley, “Turn-off transients in circular geometry MOS pass transistors,” IEEE J. Solid-State Circuits, vol. SC-21, no. 5, pp. 837–844, Oct. 1986.
11. J. S. Brugler and P. G. Jespers, “Charge pumping in MOS devices,” IEEE Trans. Electron Devices, vol. ED-16, pp. 297–302, Mar. 1969.
12. M. Declercq and P. G. Jespers, “Analysis of interface properties in MOS transistors by means of charge pumping measurement,” Electr. Telecom. SITEL, Belgium, vol. IX, no. 8, pp. 244–253, 1974.
13. F. B. Heinan and G. Warfield, “The effects of oxide traps on the MOS-capacitance,” IEEE Trans. Electron Devices, vol. ED-12, pp. 167–178, Apr. 1965.
14. S. M. Sze, Physics of Semiconductor Devices. New York: Wiley, 1981.
15. F. Rahali, “Analyse Numerique a deux Dimensions de MOST par la Methode des Elements Finis,” Ph.D. dissertation, No. 518, Swiss Federal Inst. Technol., Lausanne, 1984.
16. L. Bienstman and H. J. de Man, “An eight-channel 8-bit microprocessor compatible NMOS converter with programmable scaling,” IEEE J. Solid-State Circuits, vol. SC-15, pp. 1051–1059, Dec. 1980.
17. P. Vanpeteghem and W. Sansen, “Single versus complementary switches,” Ph.D. dissertation, Louvain la Neuve, Belgium, 1986.
18. D. J. Alstott, “A precision variable-supply CMOS comparator,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 1080–1087, Dec. 1982.
19. M. G. Degrauwe, E. A. Vittoz, and I. Verbauwhede, “A micropower CMOS instrumentation amplifier,” in ESSCIRC Dig. Tech. Papers (Edinburgh, Scotland), Sept. 1984, pp. 31–34.