A scheduler synthesis methodology for joint SW/HW design exploration of SoC

Design Automation for Embedded Systems

Volumn 14, Issue 2, 2010, Pages 75-103

  Assayad, Ismail ^a   Yovine, Sergio ^b  

^a Hassan II University of Casablanca   (Morocco)

^b UNIVERSIDAD DE BUENOS AIRES   (Argentina)

Author keywords

Exploration; Multiprocessor system on chips (SoCs); Real time requirements; Scheduling; SW HW design

Indexed keywords

COMPONENT-BASED MODELS; COMPUTING POWER; EXPLORATION; HIGH PERFORMANCE APPLICATIONS; MPEG-4 VIDEO ENCODERS; MULTI-PROCESSOR HARDWARE; MULTIMEDIA APPLICATIONS; MULTIPROCESSOR SYSTEM ON CHIPS; PARALLEL SOFTWARE; REAL TIME REQUIREMENT; SW/HW DESIGN; SYNTHESIS METHODOLOGY; SYNTHESIS TECHNIQUES; SYSTEM MODELS;

DESIGN; MOTION PICTURE EXPERTS GROUP STANDARDS; SCHEDULING; TIMING JITTER;

MULTIPROCESSING SYSTEMS;

EID: 77956912418     PISSN: 09295585     EISSN: 15728080     Source Type: Journal    
DOI: 10.1007/s10617-010-9051-5     Document Type: Article

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