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Volumn 1, Issue , 2001, Pages 217-220
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VLSI-based parallel architecture for block-matching motion estimation in low bit-rate video coding
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Author keywords
[No Author keywords available]
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Indexed keywords
BLOCK-MATCHING MOTION ESTIMATION;
LOW BIT RATE VIDEO CODING;
MOTION ESTIMATION ALGORITHM;
NEW THREE-STEP SEARCHES;
NUMBER OF GATES;
PARALLEL PROCESSING ARCHITECTURES;
THREE-STEP SEARCH;
ALGORITHMS;
IMAGE CODING;
MOTION ESTIMATION;
PARALLEL ARCHITECTURES;
TREES (MATHEMATICS);
VLSI CIRCUITS;
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EID: 77956853552
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (2)
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References (6)
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