A mixed mode perceptron cell for VLSI Neural Networks

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 1, Issue , 2001, Pages 377-380

  Camboni, Fausto ^a   Valle, Maurizio ^a  

^a UNIVERSITY OF GENOA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG INPUT SIGNALS; BUILDING BLOCKES; CMOS PROCESSS; HIGH-SPEED; LOW POWER; MIXED MODE; MIXED SIGNAL; MULTI-LAYER PERCEPTRONS; MULTIPLIER TECHNIQUES; PERCEPTRON; POWER EFFICIENCY; PROPOSED ARCHITECTURES; RE-CONFIGURABLE; SYSTEM USE;

CMOS INTEGRATED CIRCUITS; PATTERN RECOGNITION SYSTEMS; VLSI CIRCUITS; WIRELESS SENSOR NETWORKS;

NEURAL NETWORKS;

EID: 77956840803     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. J. Hertz et al., Introduction to the theory of neural Computation, Addison-Wesley, 1991, p. 327.
2. B.J. Sheu and J. Choi, Neural information processing and VLSI, Kluwer Academic Publisher, 1995, p. 559.
3. N. Saxena and J. Clark, "A Four-Quadrant CMOS Analog Multiplier for Analog Neural Networks", IEEE J. Solid-State Cicuits, vol 29, 1994, pp. 746-749.
4. D.B. Schwartz, R.E. Howard, W.E. Hubbard," A Programmable Analog Neural Network Chip", IEEE J. Solid-State Cicuits, vol. 24, 1989, pp. 313-319.
5. R. van de Plassche, Integrated Analog-to-Digital and Digital-to-Analog Converters, Kluwer Academic Publisher, 1994, p. 501.
6. C. Toumazou, F.J. Lidgey, D.G. Haigh, Analogue IC design: the current-mode approach, IEE Circuit and systems Series 2, 1990, p. 646.