A 1.1-Gb/s 115-pJ/bit configurable MIMO detector using 0.13- μm CMOS technology

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 57, Issue 9, 2010, Pages 701-705

  Liu, Liang ^a   Ye, Fan ^a   Ma, Xiaojing ^a   Zhang, Tong ^b   Ren, Junyan ^a  

^a FUDAN UNIVERSITY   (China)

^b RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

Detector; early pruned K Best; multiple inputmultiple output (MIMO); very large scale integration (VLSI)

Indexed keywords

CMOS INTEGRATED CIRCUITS; DETECTORS; ENERGY EFFICIENCY; MAXIMUM LIKELIHOOD; MIMO SYSTEMS; SIGNAL DETECTION; VLSI CIRCUITS;

DETECTION ALGORITHM; EARLY-PRUNED K-BEST; ENERGY EFFICIENT; EUCLIDEAN DISTANCE; MAXIMUM LIKELIHOOD PERFORMANCE; QUADRATIC AMPLITUDE MODULATIONS; SIGNAL DETECTORS; VERY LARGE SCALE INTEGRATION ARCHITECTURES;

QUADRATURE AMPLITUDE MODULATION;

EID: 77956712458     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2010.2058494     Document Type: Article

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