An intergrated DC-DC converter with digital one-step dead-time correction

Proceedings of the International Symposium on Power Semiconductor Devices and ICs

Volumn , Issue , 2010, Pages 57-60

  Zhao, April ^a   Shorten, Andrew ^a   Nishio, H ^b   Ng, W T ^a  

^a UNIVERSITY OF TORONTO   (Canada)

^b FUJI ELECTRIC CO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BODY-DIODE CONDUCTION; CHIP AREAS; CMOS TECHNOLOGY; DEAD-TIME CORRECTION; DEADTIME; DIGITAL CONTROL; DIGITAL CONTROLLERS; HYBRID DPWM; LEVEL SHIFTER CIRCUIT; MODULATION CIRCUITS; MOS-FET; NOR GATES; OUTPUT STAGES; POWER CONVERSION EFFICIENCIES; POWER MOSFETS; TIME OPTIMIZATION;

CMOS INTEGRATED CIRCUITS; CONVERSION EFFICIENCY; DC-DC CONVERTERS; DIGITAL CONTROL SYSTEMS; HVDC POWER TRANSMISSION; MOSFET DEVICES; OPTIMIZATION; POWER ELECTRONICS; SEMICONDUCTOR DEVICE MANUFACTURE;

SEMICONDUCTOR SWITCHES;

EID: 77956582318     PISSN: 10636854     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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