Non-robust delay test pattern generation based on stuck-at TPG

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 2001, Pages 1007-1010

  Meyer, Volker H W ^a   Anheier, Walter ^a   Sticht, Arne ^b  

^a UNIVERSITY OF BREMEN   (Germany)

^b PHILIPS RESEARCH LABORATORIES   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY FAULT SIMULATION; PATH DELAY FAULT; ROBUST DELAY TEST; ROBUST TESTS; TEST GENERATIONS; TEST PATTERN; TEST QUALITY;

TESTING;

EID: 77956439067     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. th Design Automation Conference; New Orleans, USA, June 20-22, 1977; pp. 486-491.
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3. C. J. Lin, S. M. Reddy, "On Delay Fault Testing in Logic Circuits"; IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems; CAD-6(5), 1987, pp. 694-703.
4. th Design Automation Conference, Las Vegas, USA, June 25-29, 1989; pp.351-356.
5. K.-T. Cheng, S. Devadas, K. Keutzer, "Delay-Fault Test Generation and Synthesis for Testability Under a Standard Scan Design", IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, Vol.12 No. 8, 1993, p. 1217-1231.
6. M. A. Gharabeh, M. L. Bushneil, V. D. Agrawal, "Classification and Test Generation for Path-Delay Faults using Single Stuck-Fault Tests", IEEE International Test Conference, Washington DC:, USA, Oct. 21-25, 1995; pp.139-148.
7. F. Pöhl, V. Meyer, W. Anheier; "Gate Delay Test Generation for Industrial Circuits Considering Embedded Cores"; IEEE European Test Workshop; Constance, Germany, May 25-28, 1999;.
8. K.-T. Cheng, A. Kristic, PLC Chen; "Generation of High Quality Tests for Robustly Untestable Path Delay Faults"; IEEE Trans. on Computers; 45(12), 1996, pp. 1379-1392.