Area time power estimation for FPGA based designs at a behavioral level

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 1, Issue , 2000, Pages 524-527

  Bi Lavarn, Seastien ^a   Gogniat, Guy ^a   Philippe, Jean Luc ^a  

^a LESTER   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BEHAVIORAL LEVEL; BEHAVIORAL SPECIFICATION; FPGA IMPLEMENTATIONS; PERFORMANCE ESTIMATION; POWER CONSUMPTION ESTIMATION; POWER ESTIMATIONS;

ESTIMATION;

EID: 77956055108     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2000.911593     Document Type: Conference Paper

References (9)

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8. D. Gajski, N. Dutt, A. Wu, S. Lin, "High-Level Synthesis", Kluwer Academic Publishers.
9. H. Thomas, J.P. Diguet, J.L. Philippe, "A Methodology for an Application Profiling at a System Level", SiPS, Taïwan, oct 1999.