Effect of MOSFET gate-to-drain parasitic capacitance on class-E power amplifier

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Volumn , Issue , 2010, Pages 3200-3203

  Wei, Xiuqin ^a   Sekiya, Hiroo ^a,b   Kuroiwa, Shingo ^a   Suetsugu, Tadashi ^c   Kazimierczuk, Marian K ^b  

^a CHIBA UNIVERSITY   (Japan)

^b Wright State University   (United States)

^c FUKUOKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYTICAL EXPRESSIONS; CIRCUIT EXPERIMENTS; CLASS E; CLASS-E POWER AMPLIFIERS; DESIGN EQUATION; GATE-TO-DRAIN CAPACITANCE; HIGH EFFICIENCY; INDEX TERMS; MOS-FET; OPERATING FREQUENCY; OUTPUT POWER; P-SPICE SIMULATION; PARASITIC CAPACITANCE; POWER CONVERSION EFFICIENCIES; VOLTAGE WAVEFORMS; WAVE FORMS;

CAPACITANCE; CONVERSION EFFICIENCY; FABRICS; MOS DEVICES; MOSFET DEVICES; POWER AMPLIFIERS;

SPICE;

EID: 77956001422     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2010.5537946     Document Type: Conference Paper

References (6)

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5. A. Mediano, P. M. Gaudo, and C. Bernal, "Design of class E amplifier with nonlinear and linear shunt capacitances for any duty cycle," IEEE Trans. Microwave Theory Tech., vol. 55, no. 3, pp. 484-492, Mar. 2007.
6. M. K. Kazimierczuk, RF Power Amplifiers, New York, NY: John Wiley & Sons, 2008.