A 30fps stereo matching processor based on belief propagation with disparity-parallel PE array architecture

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Volumn , Issue , 2010, Pages 453-456

  Park, Junyoung ^a   Lee, Seungjin ^a   Yoo, Hoi Jun ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAY ARCHITECTURE; BELIEF PROPAGATION; BELIEF PROPAGATION ALGORITHM; CMOS PROCESSS; DISPARITY LEVEL; MEMORY ACCESS; ON CHIP MEMORY; ON-CHIP BUFFERS; OPERATING FREQUENCY; REAL TIME STEREO; STEREO MATCHING;

CMOS INTEGRATED CIRCUITS; FABRICS; NANOTECHNOLOGY;

COMPUTER ARCHITECTURE;

EID: 77955986405     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2010.5537657     Document Type: Conference Paper

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