Sampling clock jitter estimation and compensation in ADC circuits

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Volumn , Issue , 2010, Pages 829-832

  Towfic, Zaid J ^a   Ting, Shang Kee ^a   Sayed, Ali H ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Analog to digital conversion (ADC); Clock jitter; Compensation; Interpolation

Indexed keywords

ANALOG TO DIGITAL CONVERTERS; CLOCK JITTER; CLOCK TIMING; COGNITIVE RADIO; COMPENSATION; ESTIMATION AND COMPENSATION; RANDOM PERTURBATIONS; SAMPLING CLOCK JITTER; SAMPLING CLOCKS; SAMPLING RATES; SAMPLING TIME; SUPERHETERODYNE RECEIVERS;

CLOCKS; COMPUTER SIMULATION; FABRICS; INTERPOLATION; TIME VARYING SYSTEMS;

TIMING JITTER;

EID: 77955986015     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2010.5537438     Document Type: Conference Paper

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