Fast equivalence-checking for quantum circuits

Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010

Volumn , Issue , 2010, Pages 23-28

  Yamashita, Shigeru ^a   Markov, Igor L ^b  

^a RITSUMEIKAN UNIVERSITY   (Japan)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FORMAL VERIFICATIONS; FOUR-ORDER; QUANTUM ALGORITHMS; QUANTUM CIRCUIT; REVERSIBLE CIRCUITS; RUNTIMES; VERIFICATION METHODOLOGY; VERIFICATION TECHNIQUES; VERIFICATION TOOLS;

NANOSTRUCTURED MATERIALS; QUANTUM THEORY;

LOGIC CIRCUITS;

EID: 77955814252     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NANOARCH.2010.5510932     Document Type: Conference Paper

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