Physical limitations on delay and energy dissipation of interconnects for post-CMOS devices

2010 IEEE International Interconnect Technology Conference, IITC 2010

Volumn , Issue , 2010, Pages

  Rakheja, Shaloo ^a   Naeemi, Azad ^a   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION MECHANISMS; COMPUTATIONAL POWER; DELAY PENALTY; ELECTRON CHARGE; ELECTRON SPINS; ENERGY-PER-BIT; INFORMATION PROCESSING; LOCAL INTERCONNECTS; ON CHIPS; PHYSICAL LIMITATIONS; POST-CMOS; STATE VARIABLES; TECHNOLOGY NODES;

CMOS INTEGRATED CIRCUITS; DATA PROCESSING; ELECTRON ENERGY LOSS SPECTROSCOPY; ENERGY DISSIPATION; SPIN DYNAMICS;

ENERGY DISSIPATORS;

EID: 77955596315     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2010.5510448     Document Type: Conference Paper

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