Area-efficient high-throughput VLSI architecture for MAP-based turbo equalizer

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn 2003-January, Issue , 2003, Pages 87-92

  Lee, Seok Jun ^a   Shanbhag, N R ^a   Singer, A C ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

Clocks; Computer architecture; Decoding; Delay; Equalizers; Hardware; Kernel; Silicon; Throughput; Very large scale integration

Indexed keywords

CLOCKS; CMOS INTEGRATED CIRCUITS; COMPUTER HARDWARE; DECODING; EQUALIZERS; HARDWARE; INTEGRATED CIRCUIT TESTING; QUADRATURE PHASE SHIFT KEYING; SIGNAL PROCESSING; SILICON; THROUGHPUT; VLSI CIRCUITS;

ADD-COMPARE-SELECT; CRITICAL PATH DELAYS; DELAY; HIGH THROUGHPUT; KERNEL; SOFT INPUT SOFT OUTPUT; TURBO EQUALIZERS; VLSI ARCHITECTURES;

COMPUTER ARCHITECTURE;

EID: 77955376339     PISSN: 15206130     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2003.1235649     Document Type: Conference Paper

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