Introducing a performance model for bandwidth-limited loop kernels

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 6067 LNCS, Issue PART 1, 2010, Pages 615-624

  Treibig, Jan ^a   Hager, Georg ^a  

^a UNIVERSITY OF ERLANGEN NUREMBERG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ACCURATE PERFORMANCE; DIAGNOSTIC PERFORMANCE; IN-DEPTH UNDERSTANDING; INSTRUCTION CODES; MEMORY HIERARCHY; MEMORY LOAD; MICRO ARCHITECTURES; PERFORMANCE MODEL;

EID: 77955113636     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-14390-8_64     Document Type: Conference Paper

References (5)

1. Intel Corporation: Intel 64 and IA-32 Architectures Optimization Reference Manual, Document Number: 248966-249017 (2008)
2. AMD, Inc.: Software Optimization Guide for AMD Family 10h Processors. Document Number: 40546 (2008)
3. Treibig, J., Hager, G., Wellein, G.: Multi-core architectures: Complixities of performance prediction and the impact of cache topology (2009), http://arxiv.org/abs/0910.4865
4. Schönauer, W.: Scientific Supercomputing: Architecture and Use of Shared and Distributed Memory Parallel Computers. Self-edition, Karlsruhe (2000)
5. Jalby, W., Lemuet, C., Le Pasteur, X.: WBTK: a New Set of Microbenchmarks to Explore Memory System Performance for Scientific Computing. International Journal of High Performance Computing Applications 18, 211-224 (2004)