The reverse-acceleration model for programming petascale hybrid systems

IBM Journal of Research and Development

Volumn 53, Issue 5, 2009, Pages

  Pakin, Scott ^a   Lang, Michael ^a   Kerbyson, Darren J ^a  

^a LOS ALAMOS NATIONAL LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); EMBEDDED SYSTEMS; GENERAL PURPOSE COMPUTERS; HYBRID SYSTEMS; SUPERCOMPUTERS;

ACCELERATION MODELS; CURRENT TECHNOLOGY; GENERAL PURPOSE PROCESSORS; HYBRID ARCHITECTURES; HYBRID PROGRAMMING; LOS ALAMOS NATIONAL LABORATORY; NEUTRON TRANSPORT; PERFORMANCE OPTIMIZATIONS;

ACCELERATION;

EID: 77955075376     PISSN: 00188646     EISSN: 00188646     Source Type: Journal    
DOI: 10.1147/JRD.2009.5429074     Document Type: Article

References (45)

1. K. Barker, K. Davis, A. Hoisie, D. Kerbyson, M. Lang, S. Pakin, and J. C. Sancho, "Entering the Petaflop Era: The Architecture and Performance of Roadrunner," Proceedings of the ACM/IEEE SC2008 Conference, IEEE Press, Austin, TX, November 15-21, 2008; see http://portal.acm.org/citation. cfm?id=1413372.
2. J. Michalakes and M. Vachharajani, "GPU Acceleration of Numerical Weather Prediction," Parallel Processing Lett. 18, No.4, 531-548 (2008).
3. J. C. Phillips, J. E. Stone, and K. Schulten, "Adapting a Message-Driven Parallel Application to GPU-Accelerated Clusters," Proceedings of the ACM/IEEE SC2008 Conference, IEEE Press, Austin, TX, November 15-21, 2008; see http:// portal.acm.org/citation.cfm?id=1413379.
4. J. A. Kahle, M. N. Day, H. P. Hofstee, C. R. Johns, T. R. Maeurer, and D. Shippy, "Introduction to the Cell Multiprocessor," IBM J. Res. & Dev. 49, No. 4/5, 589-604 (2005).
5. K. J. Bowers, B. J. Albright, B. K. Bergen, L. Yin, K. J. Barker, and D. J. Kerbyson, "0.374 Pflop/s Trillion-Particle Particle-in-Cell Modeling of Laser Plasma Interactions on Roadrunner," Proceedings of the ACM/IEEE SC2008 Conference, IEEE Press, Austin, TX, November 15-21, 2008; see http://portal.acm.org/citation.cfm?id=1413435.
6. S. Swaminarayan, K. Kadau, T. C. Germann, and G. C. Fossum, "369 Tflop/s Molecular Dynamics Simulations on the Roadrunner General-Purpose Heterogeneous Supercomputer," Proceedings of the ACM/IEEE SC2008 Conference, IEEE Press, Austin, TX, November 15-21, 2008; see http://portal.acm.org/citation.cfm?id=1413436.
7. A. Kumar, G. Senthilkumar, M. Krishna, N. Jayam, P. K. Baruah, R. Sharma, A. Srinivasan, and S. Kapoor, "A Buffered-Mode MPI Implementation for the Cell BE Processor," Y. Shi, G. D. van Albada, J. Dongarra, and P. M. A. Sloot, Eds., Proceedings of the 7th International Conference on Computational Science (ICCS 2007), Part I, Vol.4487, Lecture Notes in Computer Science, Beijing, China, Springer, May 27-30, 2007, pp. 603-610.
8. M. Krishna, A. Kumar, N. Jayam, G. Senthilkumar, P. Baruah, R. Sharma, S. Kapoor, and A. Srinivasan, "A Synchronous Mode MPI Implementation on the Cell BE Architecture," I. Stojmenovic, R. K. Thulasiram, L. T. Yang, W. Jia, M. Guo, and R. Fernandes de Mello, Eds., Proceedings of the 5th International Symposium on Parallel and Distributed Processing and Applications (ISPA 2007), Vol.4742, Lecture Notes in Computer Science, Niagara Falls, Canada, Springer, August 29-31, 2007, pp. 982-991.
9. M. Ohara, H. Inoue, Y. Sohda, H. Komatsu, and T. Nakatani, "MPI Microtask for Programming the Cell Broadband Engine Processor," IBM Syst. J. 45, No.1, 85-102 (2006).
10. P. Bellens, J. M. Perez, R. M. Badia, and J. Labarta, "CellSs: A Programming Model for the Cell BE Architecture," Proceedings of the ACM/IEEE SC2006 Conference (SC'06), Tampa, FL, IEEE Press, November 11-17, 2006.
11. IBM Corporation, Accelerated Library Framework Programmer's Guide and API Reference, 2009. Publication number SC33-8333-8403, product number 5724-S84, version 3, release 1.
12. Kevin O'Brien, Kathryn O'Brien, Z. Sura, T. Chen, and T. Zhang, "Supporting OpenMP on Cell," Intl. J. Parallel Programming 36, No.3, 289-311 (2008).
13. L. Dagum and R. Menon, "OpenMP: An Industry-Standard API for Shared-Memory Programming," IEEE Computational Sci. Eng. 5, No.1, 46-55 (1998).
14. J. Steed, W. Lundgren, and K. Barnes, "Gedae: A Tool for Implementing Software Radio on Heterogeneous Systems," Proceedings of the 2004 Software Defined Radio Technical Conference and Product Exposition, SDR Forum, Phoenix, AZ, November 15-18, 2004; see http://www.gedae.com/ documents/SDR%20-%20GEDAE.pdf.
15. M. D. McCool, "Data-Parallel Programming on the Cell BE and the GPU Using the RapidMind Development Platform," Proceedings of the GSPx Multicore Applications Conference, Santa Clara, CA, October 31-November 2, 2006; see http:// www.rapidmind.net/pdfs/WPdprm.pdf.
16. K. R. Koch, R. S. Baker, and R. E. Alcouffe, "Solution of the First-Order Form of the 3-D Discrete Ordinates Equation on a Massively Parallel Processor," Trans. Am. Nuclear Soc. 65, No.108, 198-199 (1992).
17. D. J. Kerbyson and A. Hoise, "A Performance Analysis of Two-Level Heterogeneous Systems on Wavefront Algorithms," E. John and J. Rubio, Eds., Unique Chips and Systems, Vol.4, Computer Engineering Series, CRC Press, November 15, 2007, pp. 259-279.
18. F. Petrini, G. Fossum, J. Fernández, A. L. Varbanescu, M. Kistler, and M. Perrone, "Multicore Surprises: Lessons Learned from Optimizing Sweep3D on the Cell Broadband Engine," Proceedings of the 21st IEEE International Parallel and Distributed Processing Symposium (IPDPS 2007), Long Beach, CA, March 26-30, 2007.
19. L. Seiler, D. Carmean, E. Sprangle, T. Forsyth, M. Abrash, P. Dubey, S. Junkins, et al., "Larrabee: A Many-Core x86 Architecture for Visual Computing," ACM Trans. Graphics (TOG) 27, No.3, 18:1-18:15 (2008).
20. S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, et al., "TILE64 Processor: A 64-core SoC with Mesh Interconnect," 2008 IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, February 3-7, 2008, pp. 88-89, 598.
21. Top500 Organization, Top500 List, June and November 2008; see http://www.top500.org/.
22. C. N. Keltcher, K. J. McGrath, A. Ahmed, and P. Conway, "The AMD Opteron Processor for Multiprocessor Servers," IEEE Micro 23, No.2, 66-76 (2003).
23. P. Harvey, R. Mandrekar, Y. Zhou, J. Zheng, J. Maloney, S. Cain, K. Kawasaki, et al., "Packaging the Cell Broadband Engine Microprocessor for Supercomputer Applications," Proceedings of the 58th Electronic Components and Technology Conference (ECTC), Lake Buena Vista, FL, May 27-30, 2008, pp. 1368-1371.
24. J. J. Dongarra, P. Luszczek, and A. Petitet, "The LINPACK Benchmark: Past, Present and Future," Concurrency and Computation: Practice and Experience, 15, No.9, 803-820 (2003).
25. C. E. Leiserson, "Fat-Trees: Universal Networks for Hardware-Efficient Supercomputing," IEEE Trans. Computers C-34, No.10, 892-901 (1985).
26. H. Jin, T. Cortes, and R. Buyya, Eds., An Introduction to the InfiniBand Architecture, Chapter 42, G. F. Pfister, High Performance Mass Storage and Parallel I/O: Technologies andApplications,Wiley Press and IEEE Press, November 26, 2001, pp. 617-632.
27. D. M. Pase and M. A. Eckl, "Performance of the AMD Opteron LS21 for IBM BladeCenter," Technical Report, IBM Corporation, Research Triangle Park, North Carolina, August 21, 2006; see ftp://ftp.software.ibm.com/eserver/ benchmarks/wp-ls21-081506.pdf.
28. T. Chen and D. A. Brokenshire, "BladeCenter QS: Maximizing Memory Performance," Technical Report, IBM Corporation, July 1, 2008; see http://www.ibm.com/ developerworks/library/pa-qsmemperf/.
29. J. Kurzak, A. Buttari, P. Luszczek, and J. Dongarra, "The PlayStation 3 for High-Performance Scientific Computing," Computing Sci. Eng. 10, No.3, 84-87 (2008).
30. S. Williams, J. Shalf, L. Oliker, S. Kamil, P. Husbands, and K. Yelick, "The Potential of the Cell Processor for Scientific Computing," Proceedings of the 3rd Conference on Computing Frontiers, Ischia, Italy, May 3-5, 2006, pp. 9-20.
31. S. Williams, J. Shalf, L. Oliker, S. Kamil, P. Husbands, and K. Yelick, "Scientific Computing Kernels on the Cell Processor," Int. J. Parallel Programming 35, No.3, 263-298 (2007).
32. M. Kistler, M. Perrone, and F. Petrini, "Cell Multiprocessor Communication Network: Built for Speed," IEEE Micro 26, No.3, 10-23 (2006).
33. K. Chang, S. Pamarti, K. Kaviani, E. Alon, X. Shi, T. J. Chin, J. Shen, et al., "Clocking and Circuit Design for a Parallel I/O on a First-Generation CELL Processor," 2005 IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, San Francisco, CA, February 6-10, 2005, pp. 526-527, 615.
34. D. Mayhew and V. Krishnan, "PCI Express and Advanced Switching: Evolutionary Path to Building Next Generation Interconnects," Proceedings of the 11th Symposium on High Performance Interconnects (HotI), Palo Alto, CA, August 20-22, 2003, pp. 21-29.
35. S. Pakin, "Receiver-Initiated Message Passing over RDMA Networks," 22nd IEEE International Parallel and Distributed Processing Symposium (IPDPS 2008), Miami, FL, April 14-18, 2008.
36. A. K. Nanda, J. R. Moulic, R. E. Hanson, G. Goldrian, M. N. Day, B. D. D'Amora, and S. Kesavarapu, "Cell/B.E. Blades: Building Blocks for Scalable, Real-Time, Interactive, and Digital Media Servers," IBM J. Res. & Dev. 51, No.5, 573-582 (2007).
37. M. Snir, S. Otto, S. Huss-Lederman, D. Walker, and J. Dongarra, MPI: The Complete Reference, Vol.1, The MPI Core, 2nd edition, MIT Press, Cambridge, MA, September 1998.
38. A. Nakano, R. K. Kalia, K. Nomura, A. Sharma, P. Vashishta, F. Shimojo, A. C. T. van Duin, et al., "De Novo Ultrascale Atomistic Simulations on High-End Parallel Supercomputers," Int. J. High Performance Computing Applic. 22, No.1, 113-128 (2008).
39. L. Peng, K. Nomura, T. Oyakawa, R. K. Kalia, A. Nakano, and P. Vashishta, "Parallel Lattice Boltzmann Flow Simulation on Emerging Multi-core Platforms," Proceedings of the 14th International Euro-Par Conference, No.5168, Lecture Notes in Computer Science, Las Palmas de Gran Canaria, Spain, Springer, August 26-29, 2008, pp. 763-777.
40. H. Dursun, K. J. Barker, D. J. Kerbyson, and S. Pakin, "Application Profiling on Cell-Based Clusters," Workshop on Large-Scale Parallel Processing (LSPP), Proceedings of the 23rd IEEE International Parallel and Distributed Processing Symposium (IPDPS), Rome, Italy, May 29, 2009 (in press).
41. A. Hoisie, O. Lubeck, and H. Wasserman, "Scalability Analysis of Multidimensional Wavefront Algorithms on Large-scale SMP Clusters," Proceedings of The 7th Symposium on the Frontiers of Massively Parallel Computation (Frontiers'99), Annapolis, MD, February 21-25, 1999, pp. 4-15.
42. O. Lubeck, M. Lang, R. Srinivasan, and G. Johnson, "Implementation and Performance Modeling of Deterministic Particle Transport (Sweep3D) on the IBM Cell/B.E.," Scientific Programming 17, No.2, 199-208 (2008).
43. IBM Corporation, C/C++ Language Extensions for Cell Broadband Engine Architecture, February 27, 2008, Version 2.5; see http://www.ibm.com/ developerworks/power/cell/ documents.html.
44. IBM Corporation, Data Communication and Sychronization for Hybrid-x86 Programmer's Guide and API Reference, October 19, 2007, publication number SC33-8408-8500, product number 5724-S84, version 3, release 0.
45. R. L. Graham, G. M. Shipman, B. W. Barrett, R. H. Castain, G. Bosilca, and A. Lumsdaine, "Open MPI: A High- Performance, Heterogeneous MPI," Fifth International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Networks (HeteroPar'06), Barcelona, Spain, September 25-28, 2006, pp. 1-9; see http:// www.open-mpi.org/papers/heteropar-2006/ heteropar-2006-paper.pdf.