Architecture design of QPP interleaver for parallel turbo decoding

IEEE Vehicular Technology Conference

Volumn , Issue , 2010, Pages

  Lee, Shuenn Gi ^a,b,c   Wang, Chung Hsuan ^a,b,c   Sheen, Wern Ho ^a,b,c  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^c CHAOYANG UNIVERSITY OF TECHNOLOGY   (Taiwan)

Author keywords

Parallel decoding; QPP interleaver; Variable interleaver lengths

Indexed keywords

ARCHITECTURE DESIGNS; CLOCK RATE; CONTENTION-FREE; CONVENTIONAL APPROACH; INTERLEAVER LENGTH; INTERLEAVERS; LARGE CIRCUITS; LOOK UP TABLE; ONLINE CALCULATIONS; PARALLEL DECODING; PARALLEL MEMORY; QUADRATIC PERMUTATION POLYNOMIALS; RE-CONFIGURABLE; TURBO CODING; TURBO DECODING;

DECODING; DESIGN; IMAGE COMPRESSION; TABLE LOOKUP;

TURBO CODES;

EID: 77954912776     PISSN: 15502252     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VETECS.2010.5493793     Document Type: Conference Paper

References (10)

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