A 1/2 × VDD to 3 × VDD bidirectional I/O buffer with a dynamic gate bias generator

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 57, Issue 7, 2010, Pages 1642-1653

  Wang, Chua Chin ^a   Hsu, Chia Hao ^a   Liu, Yi Cheng ^a  

^a NATIONAL SUN YAT SEN UNIVERSITY   (Taiwan)

Author keywords

Dynamic gate bias; floating N well; I O buffer; mixed voltage tolerant; wide range

Indexed keywords

GATES (TRANSISTOR); LOGIC DEVICES;

DYNAMIC GATE BIAS; ELECTRICAL OVERSTRESS; FLOATING N-WELL; HOT CARRIER DEGRADATION; MIXED-VOLTAGE TOLERANT; STATIC POWER CONSUMPTION; VOLTAGE CONVERTER; WIDE-RANGE;

BIAS VOLTAGE;

EID: 77954861908     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2009.2036054     Document Type: Article

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