Decomposable and responsive power models for multicore processors using performance counters

Proceedings of the International Conference on Supercomputing

Volumn , Issue , 2010, Pages 147-158

  Bertran, Ramon ^a,b   Gonzalez, Marc ^a,b   Martorell, Xavier ^a,b   Navarro, Nacho ^a,b   Ayguade, Eduard ^a,b  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b BARCELONA SUPERCOMPUTING CENTER   (Spain)

Author keywords

performance counters; power estimation

Indexed keywords

BENCHMARK SUITES; CURRENT PROCESSORS; ERROR RANGE; FREQUENCY-SCALING; LEVEL MECHANISM; MULTI-CORE PROCESSOR; MULTICORE ARCHITECTURES; ON CURRENTS; PERFORMANCE COUNTERS; PERFORMANCE MONITORING; PHASE VARIATION; POWER CONSUMPTION; POWER ESTIMATIONS; POWER MODEL; POWER MODELING; POWER-AWARE; POWER-SAVING; QUICK APPROACH; REAL SYSTEMS;

INTELLIGENT CONTROL; SOFTWARE ARCHITECTURE;

MATHEMATICAL MODELS;

EID: 77954716360     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1810085.1810108     Document Type: Conference Paper

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