Semi-automatic derivation of timing models for WCET analysis

Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)

Volumn , Issue , 2010, Pages 67-76

  Schlickling, Marc ^a   Pister, Markus ^b  

^a SAARLAND UNIVERSITY   (Germany)

^b AbsInt Angewandte Informatik GmbH   (Germany)

Author keywords

hard real time; vhdl; worst case execution time

Indexed keywords

ABSTRACT INTERPRETATIONS; ERROR-PRONE PROCESS; FLIGHT CONTROL COMPUTER; FUNCTIONAL BEHAVIORS; HARD REAL-TIME; HARD REAL-TIME SYSTEMS; HARDWARE SPECIFICATIONS; HUMAN EXPERT; HUMAN LIVES; IMPLEMENTATION ERROR; MODERN PROCESSORS; PATH CONTROL; SAFETY CRITICAL SYSTEMS; SEMI-AUTOMATICS; SYSTEM CONTROLLERS; TIMING CONSTRAINTS; TIMING MODELS; UPPER BOUND; VERILOG; WORST-CASE EXECUTION TIME;

ABSTRACTING; AIRCRAFT CONTROL; COMPUTER CONTROL SYSTEMS; COMPUTER HARDWARE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; CONTROL SYSTEM STABILITY; EMBEDDED SYSTEMS; FLIGHT PATHS; LINGUISTICS; MATHEMATICAL MODELS; NANOTECHNOLOGY; PROGRAM COMPILERS; SECURITY SYSTEMS; SPECIFICATIONS; TIME MEASUREMENT; TIMING CIRCUITS;

REAL TIME SYSTEMS;

EID: 77954480358     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1755888.1755899     Document Type: Conference Paper

References (37)

1. AbsInt Angewandte Informatik GmbH, The Program Analyzer Generator User's Manual, 2002.
2. AbsInt Angewandte Informatik GmbH, aiSee. Graph Visualization User's Documentation, 2005.
3. P. J. Ashenden, The Designer's Guide to VHDL, Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 2001.
4. G. Bernat, A. Burns, and M. Newby, Probabilistic timing analysis: An approach using copulas, Journal of Embedded Computing 1 (2005), no. 2, 179-194.
5. Mentor Graphics Corporation, ModelSim User's Manual, May 2008.
6. P. Cousot, Abstract Interpretation Based Formal Methods and Future Challenges, invited paper, Informatics - 10 Years Back, 10 Years Ahead (R. Wilhelm, ed.), Lecture Notes in Computer Science, vol. 2000, Springer, 2001, pp. 138-156.
7. P. Cousot and R. Cousot, Abstract Interpretation: a Unified Lattice Model for Static Analysis of Programs by Construction or Approximation of Fixpoints, Conference Record of the Fourth Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages (Los Angeles, California), ACM Press, New York, NY, 1977, pp. 238-252.
8. P. Cousot and R. Cousot, Abstract Interpretation and Application to Logic Programs, Journal of Logic Programming 13 (1992), no. 2&3, 103-179.
9. A. Ermedahl, A Modular Tool Architecture for Worst-Case Execution Time Analysis, Ph.D. thesis, Uppsala University, 2003.
10. C. Ferdinand and R. Heckmann, aiT: Worst-Case Execution Time Prediction by Static Programm Analysis, Building the Information Society. IFIP 18th World Computer Congress (R. Jacquart, ed.), Kluwer, 2004, pp. 377-384.
11. C. Ferdinand, R. Heckmann, M. Langenbach, F. Martin, M. Schmidt, H. Theiling, S. Thesing, and R. Wilhelm, Reliable and Precise WCET Determination for a Real-Life Processor, Proceedings of the First International Workshop on Embedded Software (EMSOFT 2001) (Berlin) (Thomas A. Henzinger and Christoph M. Kirsch, eds.), Lecture Notes in Computer Science, vol. 2211, Springer, 2001, pp. 469-485.
12. C. Ferdinand, F. Martin, C. Cullmann, M. Schlickling, I. Stein, S. Thesing, and R. Heckmann, New Developments in WCET Analysis, Program Analysis and Compilation. Theory and Practice. Essays Dedicated to Reinhard Wilhelm on the Occasion of His 60th Birthday (T. Reps, M. Sagiv, and J. Bauer, eds.), Lecture Notes in Computer Science, vol. 4444, Springer, 2007, pp. 12-52.
13. C. Ferdinand, F. Martin, R. Wilhelm, and M. Alt, Cache Behavior Prediction by Abstract Interpretation, Science of Computer Programming 35 (1999), no. 2, 163-189.
14. J. Gaisler, Leon2 Processor User's Manual - version 1.0.30, July 2005.
15. N. Holsti, T. Långbacka, and S. Saarinen, Worst-Case Execution Time Analysis, Proceedings of the European Conference on Signal Processing (EUSIPCO 2000), 2000.
16. Freescale Semiconductor Inc., MPC750 RISC Microprocessor Family User's Manual, December 2001.
17. Institute of Electrical and Electronics Engineers, New York, IEEE Standard P1076.6 1999 VHDL Register Transfer Level Synthesis, 1999.
18. Institute of Electrical and Electronics Engineers, New York, IEEE Standard P1076 2000 VHDL Language Reference Manual, 2000.
19. D. Kästner, R. Wilhelm, R. Heckmann, M. Schlickling, M. Pister, M. Jersak, K. Richter, and C. Ferdinand, Timing Validation of Automotive Software, 3rd International Symposium on Leveraging Applications of Formal Methods, Verification and Validation (ISOLA) 2008 (T. Margaria and B. Steffen, eds.), Communications in Computer and Information Science, vol. 17, Springer, 2008, pp. 93-107.
20. R. Kirner, R. Lang, G. Freiberger, and P. Puschner, Fully Automatic Worst-Case Execution Time Analysis for Matlab/Simulink Models, Proceedings of the 14th Euromicro Conference on Real-Time Systems (ECRTS 2002), IEEE Computer Society, 2002, pp. 31-40.
21. M. Langenbach, CRL - A Uniform Representation for Control Flow, Tech. report, Saarland University, 1998.
22. X. Li, Y. Liang, T. Mitra, and A. Roychoudhury, Chronos: A timing analyzer for embedded software, Science of Computer Programming 69 (2007), no. 1-3, 56-67, Special issue on Experimental Software and Toolkits.
23. ARM Limited, ARM Architecture Reference Manual, June 2000.
24. T. Lundqvist and P. Stenström, An Integrated Path and Timing Analysis Method based on Cycle-Level Symbolic Execution, Real-Time Syst. 17 (1999), no. 2-3, 183-207.
25. M. A. Maksoud, M. Pister, and M. Schlickling, An Abstraction-Aware Compiler for VHDL Models, Proceedings of the International Conference on Computer Engineering and Systems (ICCES '09), IEEE Computer Society, December 2009, pp. 3-9.
26. F. Martin, Generating Program Analyzers, Ph.D. thesis, Saarland University, 1999.
27. F. Nielson, H. R. Nielson, and C. Hankin, Principles of Program Analysis, Springer, 1999.
28. P. Puschner and R. Nossal, Testing the Results of Static Worst-Case Execution-Time Analysis, IEEE Real-Time Systems Symposium, 1998, pp. 134-143.
29. M. Schlickling and M. Pister, A Framework for Static Analysis of VHDL Code, Proceedings of 7th International Workshop on Worst-Case Execution Time Analysis (WCET 2007) (C. Rochange, ed.), Internationales Begegnungs- und Forschungszentrum für Informatik (IBFI), Schloss Dagstuhl, Germany, 2007.
30. M. Sicks, Adreßbestimmung zur Vorhersage des Verhaltens von Daten-Caches, Master's thesis, Saarland University, 1997.
31. J. Souyris, E. Le Pavec, G. Himbert, V. Jégu, G. Borios, and R. Heckmann, Computing the Worst Case Execution Time of an Avionics Program by Abstract Interpretation, Proceedings of the 5th International Workshop on Worst-case Execution Time (WCET 2005), 2005, pp. 21-24.
32. T. Gingold, GHDL. A VHDL compiler, 2007.
33. S. Thesing, Safe and Precise WCET Determination by Abstract Interpretation of Pipeline Models, Ph.D. thesis, Saarland University, 2004.
34. S. Thesing, Modeling a System Controller for Timing Analysis, Proceedings of the 6th ACM & IEEE International conference on Embedded software (EMSOFT 2006) (S. L. Min and W. Yi, eds.), ACM, 2006, pp. 292-300.
35. M. Weiser, Program Slicing, IEEE Transaction in Software Engineering 10 (1984), no. 4, 352-357.
36. R. Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing, D. Whalley, G. Bernat, C. Ferdinand, R. Heckmann, F. Mueller, I. Puaut, P. Puschner, J. Staschulat, and P. Stenström, The Worst-Case Execution Time Problem - Overview of Methods and Survey of Tools, 7 (2008), no. 3.
37. R. Wilhelm, D. Grund, J. Reineke, M. Schlickling, M. Pister, and C. Ferdinand, Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-critical Embedded Systems, IEEE Transactions on CAD of Integrated Circuits and Systems 28 (2009), no. 7, 966-978.