Parallelization schemes for memory optimization on the cell processor: A case study of image processing algorithm

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2007, Pages 9-16

  Saidani, Tarik ^a   Piskorski, Stéphane ^b   Lacassagne, Lionel ^a   Bouaziz, Samir ^a  

^a UNIV PARIS SUD   (France)

^b UFR 919 Laboratoire d'Informatique Pour la Mécanique et les Sciences de l'Ingénieur   (France)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION DEVELOPERS; CELL PROCESSOR; EFFECTIVE PERFORMANCE; HARRIS ALGORITHM; HETEROGENEOUS MULTIPROCESSORS; IMAGE PROCESSING ALGORITHM; IMAGE PROCESSING APPLICATIONS; MEDIA APPLICATION; MEMORY OPTIMIZATION; MULTICORE ARCHITECTURES; ON CHIPS; PARALLEL SCHEME; PARALLELIZATIONS; PEAK PERFORMANCE; POINTS OF INTEREST; SOFTWARE TOOL;

DATA TRANSFER; IMAGE PROCESSING; IMAGING SYSTEMS; NANOTECHNOLOGY;

COMPUTER ARCHITECTURE;

EID: 77954433878     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1327171.1327172     Document Type: Conference Paper

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