Scalability of sub-100 nm InAs HEMTs on InP substrate for future logic applications

IEEE Transactions on Electron Devices

Volumn 57, Issue 7, 2010, Pages 1504-1511

  Kim, Dae Hyun ^a   Del Alamo, Jesús A ^b  

^a TELEDYNE SCIENTIFIC COMPANY   (United States)

^b USA   (United States)

Author keywords

Drain induced barrier lowering (DIBL); gate delay; high electron mobility transistor (HEMT); IONOFF; InAs; logic; scaling; subthreshold swing

Indexed keywords

BAND TO BAND TUNNELING; BARRIER LOWERING; DRAIN-INDUCED BARRIER LOWERING; FIGURES OF MERITS; GATE DELAYS; GATE LENGTH; HIGH FREQUENCY OPERATION; INALAS; INAS; INP SUBSTRATES; LOGIC APPLICATIONS; LOGIC GATE DELAY; LOGIC OPERATIONS; NARROW BAND GAP; NMOSFET; SCALING BEHAVIOR; SI DEVICES; SUB-100 NM; SUBCHANNELS; SUBTHRESHOLD SWING;

ELECTRON MOBILITY; FIELD EFFECT TRANSISTORS; SCALABILITY; SEMICONDUCTING INDIUM;

HIGH ELECTRON MOBILITY TRANSISTORS;

EID: 77954029766     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2010.2049075     Document Type: Article

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