Low-sensitivity to process variations aging sensor for automotive safety-critical applications

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2010, Pages 238-243

  Vazquez, J C ^a,b   Champac, V ^b   Ziesemer Jr , A M ^a,c   Reis, R ^c   Teixeira, I C ^a,d   Santos, M B ^a,d   Teixeira, J P ^a,d  

^a INESC ID   (Portugal)

^b INSTITUTO NACIONAL DE ASTROFÍSICA   (Mexico)

^c FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

^d INSTITUTO SUPERIOR TÉCNICO   (Portugal)

Author keywords

Aging sensors; Failure prediction; Process variations; Reliability in nanometer technologies

Indexed keywords

AGING MONITORING; AGING PROCESS; AREA OVERHEAD; AUTOMOTIVE MARKETS; AUTOMOTIVE SAFETY; CIRCUIT FAILURES; CIRCUIT OPERATION; DELAY FAULTS; DEVICE-SCALING; FAILURE PREDICTION; KEY LOCATION; LOW SENSITIVITY; NANOMETER TECHNOLOGY; ON CHIPS; PHYSICAL DEFECTS; POWER SUPPLY VOLTAGE; PROCESS VARIATION; PROGRAMMABLE DELAY; SAFE OPERATION; SAFETY-CRITICAL; SENSOR DESIGNS; SIMULATION RESULT;

DECISION MAKING; FORECASTING; RELIABILITY; SENSITIVITY ANALYSIS; TIMING CIRCUITS;

SENSORS;

EID: 77953883911     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2010.5469568     Document Type: Conference Paper

References (25)

1. J. Tschanz, et al. "Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging," Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC'07), pp. 292-293, 2007.
2. J.W. McPherson, "Reliability Challenges for 45 nm and Beyond", Proc. ACM/IEEE Design Autom. Conf. (DAC), pp. 176-181, 2006.
3. H. Ahrens, et al., "DFT Architecture for Automotive Microprocessors using On-chip Scan Compression supporting Dual Vendor ATPG", Proc. IEEE Int. Test Conf. (ITC), paper 18.3, 2008.
4. B. C. Paul et al., "Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits", Proc. DATE, pp. 780-785, 2006.
5. D. Pan et al., "A Radiation-hard Phase-Locked Loop", Proc. IEEE Int. Symp. on Industrial Electronics (ISIE), vol. 2, pp. 901- 906, 2003.
6. th. Annual International Reliabilty Physics Symposium, pp. 248-254, 2002.
7. V. Reddy, et al., "The Impact of NBTI on the Performance of Combinational and Sequential Circuits", Proc. ACM/IEEE Design Automation Conf. (DAC), pp. 364-369, 2007.
8. R. Vattikonda, W. Wang, Y. Cao, "Modeling and Minimization of PMOS NBTI Effect for Robust Nanometer Design", Proc. DAC, pp. 1047-1052, 2006.
9. K. Kang, S. Gangwal, S.P. Park, K. Roy, "NBTI Induced Performance Degradation in Logic and Memory Circuits: How Effectively Can We Approach a Reliability Solution?", Proc. IEEE Asia-South Pacific Design Automation Conference (ASP-DAC), pp. 726-731, 2008.
10. W. Wang, Z. Wei, Sh. Yang, Y. Cao, "An Efficient Method to Identify Critical Gates under Circuit Aging", Proc. IEEE Int. Conf. on CAD (ICCAD), pp. 735-740, 2007.
11. M. Agarwal, et al., "Circuit Failure Prediction and Its Application to Transistor Aging". Proc. VLSI Test Symp. (VTS), pp. 277-286, 2007.
12. S.V. Kumar, C.H. Kim, S. Sapatnekar, "Adaptive Techniques for Overcoming Performance Degradation due to Aging in Digital Circuits", Proc. IEEE ASP-DAC, pp. 284-289, Jan. 2009.
13. M. Agarwal et al., "Optimized Circuit Failure Prediction for Aging: Practicality and Promise", Proc. ITC, paper 26.1, 2008.
14. Z. Qi, M.R. Stan, "NBTI Resilient Circuits Using Adaptive Body Biasing", Proc. ACM Great Lakes VLSI Symosium., pp. 285-290, 2008.
15. J. C. Vazquez et al., "Built-In Aging Monitoring for Safety-Critical Applications", Proc. of the IEEE Int. On-Line Test Symposium (IOLTS), pp. 9-14, June, 2009.
16. J. C. Vazquez et al., "Programmable Aging Sensor for Automotive Safety-Critical Applications", Proc. DATE, 2010.
17. C. Metra et al., "Self-Checking Detection and Diagnosis Scheme for Transient, Delay and Crosstalk Faults Affecting Bus Lines", IEEE Trans. on Computers, vol. 49, no. 6, pp. 560-574, June 2000.
18. S. Ghosh et al., "A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor", IEEE Trans. CAD of Int. C&S, vol. 25, no. 12, pp. 2934-2943, 2006.
19. Bo Shen, Sunil P. Khatri, Takis Zourntos, "Implementation of MOSFET based Capacitors for Digital Applications", Proc. Great Lakes VLSI Symp. (GLSVLSI), pp. 180-185, 2006.
20. XTRAN Fleet Management System, TecMic™ product (http://www.tecmic. pt/eng/xtran/xtran-intro.html) 2009.
21. Predictive Technology Model (PTM), http://www.eas.asu.edu/~ptm/ .
22. C. Park, et al., "Reversal of temperature dependence of integrated circuits operating at very low voltages," Proc. Int. Electron Devices Meeting (IEDM'95), pp. 71-74, Dec. 1995.
23. A. Bellaouar et al., "Supply voltage scaling for temperature insensitive CMOS circuit operation," IEEE Trans. Circ. and Syst.-II: Analog Dig. Signal Processing, vol. 45, no. 3, pp. 415-417, 1998.
24. Int. Technology Roadmap for Semiconductors, http://www.itrs.net/
25. A. Ziesemer Jr., C. Lazzari, R. Reis, "Transistor level automatic layout generator for non-complementary CMOS cells", Proc. VLSI-SOC, pp. 116-121, 2007.