Optimizing correctly-rounded reciprocal square roots for embedded VLIW cores

Conference Record - Asilomar Conference on Signals, Systems and Computers

Volumn , Issue , 2009, Pages 731-735

  Jeannerod, Claude Pierre ^a,b,c   Revy, Guillaume ^a,b,c  

^a INRIA RHÔNE ALPES   (France)

^b UNIVERSITÉ DE LYON   (France)

^c UNIVERSITÉ DE LYON   (France)

Author keywords

Binary floating point arithmetic; Correct rounding (to nearest); Polynomial evaluation; Reciprocal square root; Software implementation; Vliw processor core

Indexed keywords

FLOATING-POINT ARITHMETIC; POLYNOMIAL EVALUATION; SOFTWARE IMPLEMENTATION; SQUARE ROOTS; VLIW PROCESSOR;

DIGITAL ARITHMETIC; NANOTECHNOLOGY; OPTIMIZATION; POLYNOMIAL APPROXIMATION; VERY LONG INSTRUCTION WORD ARCHITECTURE;

COMPUTER SOFTWARE SELECTION AND EVALUATION;

EID: 77953851557     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ACSSC.2009.5469948     Document Type: Conference Paper

References (11)

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