High-gain double-bulk mixer in 65 nm CMOS with 830 μW power consumption

ETRI Journal

Volumn 32, Issue 3, 2010, Pages 457-459

  Schweiger, Kurt ^a   Zimmermann, Horst ^a  

^a VIENNA UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

Bulk mixer; Down sampling mixer; Low power; Nanometer cmos

Indexed keywords

65NM CMOS TECHNOLOGY; DOWNSAMPLING; HIGH-GAIN; LOW POWER; NANOMETER CMOS; POWER CONSUMPTION; SUPPLY VOLTAGES;

CMOS INTEGRATED CIRCUITS; MIXING;

MIXERS (MACHINERY);

EID: 77953453525     PISSN: 12256463     EISSN: None     Source Type: Journal    
DOI: 10.4218/etrij.10.0209.0504     Document Type: Article

References (6)

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4. K. Schweiger and H. Zimmermann, "Low-Voltage Low-Power Highly Linear Down-Sampling Mixer in 65 nm Digital CMOS Technology," Proc. Design Diagnostics Electron. Circuits Syst., April 2008, pp. 1-4.
5. C. Kienmayer et al., "A Low-Power Low-Voltage NMOS Bulk-Mixer with 20 GHz Bandwidth in 90 nm CMOS," IEEE Int. Symp. Circuits Syst., vol. 4, May 2004, pp. 385-388.
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