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Volumn 4, Issue 3, 2010, Pages 159-169

MetaWire: Using FPGA configuration circuitry to emulate a network-on-chip

Author keywords

[No Author keywords available]

Indexed keywords

FPGA CONFIGURATION; GLOBAL NETWORKS; INTERNAL CONFIGURATION ACCESS PORTS; NETWORK ON CHIP; NETWORKS ON CHIPS; PERFORMANCE PENALTIES; PROOF OF CONCEPT; RECONFIGURABLE NETWORK; RECONFIGURABLE STRUCTURE; SYSTEM OPERATION; XILINX FPGA;

EID: 77953330975     PISSN: 17518601     EISSN: None     Source Type: Journal    
DOI: 10.1049/iet-cdt.2009.0009     Document Type: Article
Times cited : (8)

References (11)
  • 1
    • 0034848112 scopus 로고    scopus 로고
    • Route packets, not wires: on-chip interconnection networks
    • Las Vegas, Nevada, USA, June
    • Dally, W.J. Towles, B.: 'Route packets, not wires: on-chip interconnection networks', Proc. Conf. on Design Automation, Las Vegas, Nevada, USA, June 2001, p. 684-689
    • (2001) Proc. Conf. on Design Automation , pp. 684-689
    • Dally, W.J.1    Towles, B.2
  • 3
    • 3042740415 scopus 로고    scopus 로고
    • Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip
    • Paris, France, February
    • Millberg, M. Nilsson, E. Thid, R. Jantsch, A.: 'Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip', Proc. Design, Automation and Test in Europe Conf. and Exhibition, Paris, France, February 2004, 2, p. 890-895
    • (2004) Proc. Design, Automation and Test in Europe Conf. and Exhibition , vol.2 , pp. 890-895
    • Millberg, M.1    Nilsson, E.2    Thid, R.3    Jantsch, A.4
  • 4
    • 84893753441 scopus 로고    scopus 로고
    • Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip
    • Munich, Germany, March
    • Rijpkema, E. Goossens, K. Raüdulescu, A.: et al. 'Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip', Proc. Design, Automation and Test in Europe Conf. and Exhibition, Munich, Germany, March 2003, p. 350-355
    • (2003) Proc. Design, Automation and Test in Europe Conf. and Exhibition , pp. 350-355
    • Rijpkema, E.1    Goossens, K.2    Raüdulescu, A.3
  • 6
    • 36349011341 scopus 로고    scopus 로고
    • NoC-based FPGA: Architecture and routing
    • Princeton, New Jersey, USA, May
    • Gindin, R. Cidon, I. Keidar, I.: 'NoC-based FPGA: Architecture and routing', Proc. Int. Symp. on Networks-on-Chip, Princeton, New Jersey, USA, May 2007, p. 253-264
    • (2007) Proc. Int. Symp. on Networks-on-Chip , pp. 253-264
    • Gindin, R.1    Cidon, I.2    Keidar, I.3
  • 7
    • 77953333483 scopus 로고    scopus 로고
    • Improving field-programmable gate array scaling through wire emulation September, 2004, Master's, Virginia Tech Blacksburg, Virginia, USA
    • Fong, R.: 'Improving field-programmable gate array scaling through wire emulation', September, 2004, Master's, Virginia Tech Blacksburg, Virginia, USA
    • Fong, R.1
  • 8
    • 77953327882 scopus 로고    scopus 로고
    • Xilinx, Inc.: 'Virtex-4 Family Overview'. Available at: http://www.xilinx.com/support/documentation/data_sheets/ds112.pdf, September 2007 [Online]
    • Xilinx, Inc.: 'Virtex-4 Family Overview'. Available at: http://www.xilinx.com/support/documentation/data_sheets/ds112.pdf, September 2007 [Online]
  • 9
    • 77953337540 scopus 로고    scopus 로고
    • Xilinx, Inc.: 'Virtex-4 Configuration Guide'. Available at: http://www.xilinx.com/support/documentation/user_guides/ug071.pdf, October 2007 [Online]
    • Xilinx, Inc.: 'Virtex-4 Configuration Guide'. Available at: http://www.xilinx.com/support/documentation/user_guides/ug071.pdf, October 2007 [Online]
  • 10
    • 48149113769 scopus 로고    scopus 로고
    • Wires on demand: run-time communication synthesis for reconfigurable computing
    • Amsterdam, Netherlands, August
    • Athanas, P. Bowen, J. Dunham, T.: et al. 'Wires on demand: run-time communication synthesis for reconfigurable computing', Proc. Int. Conf. on Field Programmable Logic and Applications, Amsterdam, Netherlands, August 2007, p. 513-516
    • (2007) Proc. Int. Conf. on Field Programmable Logic and Applications , pp. 513-516
    • Athanas, P.1    Bowen, J.2    Dunham, T.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.