FPGA based parallel architectures for normalized cross-correlation

2009 1st International Conference on Information Science and Engineering, ICISE 2009

Volumn , Issue , 2009, Pages 225-229

  Wang, Xiaotao ^a   Wang, Xingbo ^b  

^a NANJING UNIVERSITY OF AERONAUTICS AND ASTRONAUTICS   (China)

^b SHANDONG UNIVERSITY   (China)

Author keywords

FPGA; Image matching; Normalized cross correlation; Parallel architecture

Indexed keywords

COMPUTATION TIME; DEDICATED HARDWARE; FPGA CHIPS; HIGH-SPEED; LOGIC RESOURCES; NORMALIZED CROSS-CORRELATION; QUARTUS II; REAL-TIME IMPLEMENTATIONS; SIMILARITY MEASURE; SPEED PERFORMANCE; TARGET MATCHING; TARGET RECOGNITION;

HARDWARE; IMAGE MATCHING; IMAGE PROCESSING; INFORMATION SCIENCE; PARALLEL ARCHITECTURES; REAL TIME CONTROL; TARGETS;

CORRELATION METHODS;

EID: 77952773298     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICISE.2009.603     Document Type: Conference Paper

References (6)

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3. Altera Corporation, Stratix II Device Handbook, May 2007.
4. Almudena Lindoso, Luis Entrena. High performance FPGA-based image correlation, J. Real-Time Image Proc. 2007, vol. 2, pp.223-233
5. Altera Corporation, Quartus II Version 8.0 Handbook, 2008.
6. Analog Devices Inc., "TigerSHARC Embedded Processor ADSP-TS201S," 2006.