Visualizing complex dynamics in many-core accelerator architectures

ISPASS 2010 - IEEE International Symposium on Performance Analysis of Systems and Software

Volumn , Issue , 2010, Pages 164-174

  Ariel, Aaron ^a   Fung, Wilson W L ^a   Turner, Andrew E ^a   Aamodt, Tor M ^a  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ACCELERATOR ARCHITECTURES; ANOMALOUS BEHAVIOR; APPLICATION EXECUTION; ARCHITECTURE DESIGNS; COMPLEX DYNAMIC BEHAVIOR; COMPLEX DYNAMICS; COMPUTING POWER; DYNAMIC BEHAVIORS; GRAPHICS PROCESSING UNITS; HARDWARE DESIGNERS; IDENTIFICATION PROCESS; MANY-CORE; MASSIVE PARALLELISM; NOVEL METHODOLOGY; ORDERS OF MAGNITUDE; PERFORMANCE ANALYSIS; PERFORMANCE COUNTERS; PERFORMANCE LOSS; PERFORMANCE POTENTIALS; PERFORMANCE STATISTICS; PERFORMANCE VISUALIZATION; SOFTWARE DEVELOPER; SOURCE CODES;

OPTIMIZATION; VISUALIZATION;

PROGRAM PROCESSORS;

EID: 77952660587     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2010.5452029     Document Type: Conference Paper

References (44)

1. "Open|SpeedShop." [Online]. Available: http://www. openspeedshop.org/wp/
2. ATI CTM Guide, 1st ed., Advanced Micro Devices, Inc., 2006.
3. Press Release: AMD Delivers Enthusiast Performance Leadership with the Introduction of the ATI Radeon HD 3870 X2, http://www.amd.com, Advanced Micro Devices, Inc., 28 January 2008.
4. S. Al-Kiswany, "Personal Communication," 2009.
5. S. Al-Kiswany, A. Gharaibeh, E. Santos-Neto, G. Yuan, and M. Ripeanu, "StoreGPU: Exploiting Graphics Processing Units to Accelerate Distributed Storage Systems," in Proc. 17th Int'l Symp. on High Performance Distributed Computing, 2008, pp. 165-174.
6. A. R. Alameldeen and D. A. Wood, "Variability in architectural simulations of multi-threaded workloads," in Proc. 9th Int'l Symp. on High Performance Computer Architecture, 2003, pp. 7-18.
7. A. Alexandrov, S. Bratanov, J. Fedorova, D. Levinthal, I. Lopatin, and D. Ryabtsev, "Parallelization Made Easier with Intel Performance-Tuning Utility," Intel Technology Journal, vol.11, no.4, 2007.
8. Apple Inc., "Optimizing with Shark." [Online]. Available: http://developer.apple.com/tools/shark optimize.html
9. A. Bakhoda, G. L. Yuan, W. W. L. Fung, H. Wong, and T. M. Aamodt, "Analyzing CUDA Workloads Using a Detailed GPU Simulator," in IEEE Int'l Symp. on Performance Analysis of Systems and Software (ISPASS 2009), April 2009, pp. 163-174.
10. M. Biberstein, U. Shvadron, J. Turek, B. Mendelson, and M. Chang, "Trace-based Performance Analysis on Cell BE," in IEEE Int'l Symp. on Performance Analysis of Systems and Software (ISPASS 2008), April 2008, pp. 213-222.
11. D. Burger and T. M. Austin, "The SimpleScalar Tool Set, Version 2.0," http://www.simplescalar.com, 1997.
12. CEPBA, "Paraver - Parallel Program Visualization and Analysis tool - REFERENCE MANUAL," 2001.
13. D. Dale, M. Droettboom, E. Firing, and J. Hunter, "Matplotlib User's Guide," http://matplotlib.sourceforge.net/Matplotlib.pdf.
14. W. W. L. Fung, I. Sham, G. Yuan, and T. M. Aamodt, "Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow," in Proc. 40th IEEE/ACM Int'l Symp. on Microarchitecture, 2007.
15. -, "Dynamic Warp Formation: Efficient MIMD Control Flow on SIMD Graphics Hardware," ACM Trans. Archit. Code Optim., vol.6, no.2, pp. 1-37, 2009.
16. M. Giles and S. Xiaoke, "Notes on Using the NVIDIA 8800 GTX Graphics Card." [Online]. Available: http://people.maths.ox.ac.uk/ ~gilesm/hpc/
17. P. Harish and P. J. Narayanan, "Accelerating Large Graph Algorithms on the GPU Using CUDA," in HiPC, 2007, pp. 197-208.
18. M. Harris, "UNSW CUDA Tutorial Part 4 - Optimizing CUDA." [Online]. Available: http://www.cse.unsw.edu.au/~pls/cuda-workshop09/slides/04 OptimizingCUDA full.pdf
19. S. Hong and H. Kim, "An Analytical Model for a GPU Architecture with Memory-Level and Thread-Level Parallelism Awareness," Proc. 36th Int'l Symp. on Computer Architecture, vol.37, no.3, pp. 152-163, 2009.
20. Intel Corp., "Intel VTune™ Performance Analyzer." [Online]. Available: http://software.intel.com/en-us/intel-vtune/
21. OpenCL 1.0 Specification, 1st ed., Khronos Group, 2009.
22. A. Levinthal and T. Porter, "Chap - a SIMD Graphics Processor," in Proc. 11th Conf. on Computer Graphics and Interactive Techniques (SIGGRAPH '84), 1984, pp. 77-82.
23. E. Lindholm, J. Nickolls, S. Oberman, and J. Montrym, "NVIDIA Tesla: A Unified Graphics and Computing Architecture," IEEE Micro, vol.28, no.2, pp. 39-55, 2008.
24. Marco Chiappetta, "ATI Stream Computing: ATI Radeon™ HD 3800/4800 Series GPU Hardware Overview." [Online]. Available: http://developer.amd.com/gpu/ATIStreamSDK/pages/Publications.aspx
25. Maxime, "Ray tracing," http://www.nvidia.com/cuda.
26. J. Meng, D. Tarjan, and K. Skadron, "Leveraging Memory Level Parallelism Using Dynamic Warp Subdivision," Department of Computer Science, University of Virginia, Tech. Rep. CS-2009-2102, 2009.
27. J. Merino, L. Alvarez, M. Gil, and N. Navarro, "Cetra: A Trace and Analysis Framework for the Evaluation of Cell BE systems," in IEEE Int'l Symp. on Performance Analysis of Systems and Software (ISPASS 2009), April 2009, pp. 43-52.
28. J. Nickolls, I. Buck, M. Garland, and K. Skadron, "Scalable Parallel Programming with CUDA," ACM Queue, vol.6, no.2, pp. 40-53, Mar.-Apr. 2008.
29. NVIDIA CUDA Visual Profiler, 1st ed., NVIDIA Corp., 2008. [Online]. Available: http://developer.download.nvidia.com/compute/cuda/2 3/toolkit/docs/cudaprof 2.3 readme.txt
30. NVIDIA Corporation, "NVIDIA CUDA SDK code samples." [Online]. Available: http://developer.download.nvidia.com/compute/cuda/sdk/website/ samples.html
31. NVIDIA CUDA Programming Guide, 1st ed., NVIDIA Corporation, 2007.
32. Press Release: NVIDIA Tesla GPU Computing Processor Ushers In the Era of Personal Supercomputing, http://www.nvidia.com, NVIDIA Corporation, 20 June 2007.
33. Rice University, "HPCToolkit." [Online]. Available: http://hpctoolkit.org/
34. S. Rixner, W. J. Dally, U. J. Kapasi, P. Mattson, and J. D. Owens, "Memory Access Scheduling," in Proc. 27th Int'l Symp. on Computer Architecture, 2000, pp. 128-138.
35. S. Ryoo, C. Rodrigues, S. Stone, S. Baghsorkhi, S.-Z. Ueng, J. Stratton, and W. W. Hwu, "Program Optimization Space Pruning for a Multithreaded GPU," in Proc. 6th Int'l Symp. on Code Generation and Optimization (CGO), April 2008, pp. 195-204.
36. M. Schatz, C. Trapnell, A. Delcher, and A. Varshney, "High- Throughput Sequence Alignment Using Graphics Processing Units," BMC Bioinformatics, vol.8, no.1, p. 474, 2007. [Online]. Available: http://www.biomedcentral.com/1471-2105/8/474
37. S. S. Shende and A. D. Malony, "The TAU Parallel Performance System," Int. J. High Perform. Comput. Appl., vol.20, no.2, pp. 287-311, 2006.
38. Sun Microsystems, "Sun Studio Performance Analyzer." [Online]. Available: http://developers.sun.com/sunstudio/
39. N. R. Tallent, J. M. Mellor-Crummey, L. Adhianto, M. W. Fagan, and M. Krentel, "Diagnosing Performance Bottlenecks in Emerging Petascale Applications," in ACM/IEEE Conference on Supercomputing (SC'09). ACM, 2009, pp. 1-11.
40. N. R. Tallent, J. M. Mellor-Crummey, and M. W. Fagan, "Binary Analysis for Measurement and Attribution of Program Performance," in Proc. ACM SIGPLAN Conf. on Programming Language Design and Implementation (PLDI'09), 2009, pp. 441-452.
41. D. Tarjan, J. Meng, and K. Skadron, "Increasing Memory Miss Tolerance for SIMD Cores," in ACM/IEEE Conference on Supercomputing (SC'09), 2009.
42. C. Weaver, K. C. Barr, E. Marsman, D. Ernst, and T. Austin, "Performance Analysis Using Pipeline Visualization," in Performance Analysis of Systems and Software, 2001. ISPASS. 2001 IEEE Int'l Symp. on, 2001, pp. 18-21.
43. G. Yuan, "Personal Communication," 2009.
44. G. L. Yuan, A. Bakhoda, and T. M. Aamodt, "Complexity Effective Memory Access Scheduling for Many-Core Accelerator Architectures," in Proc. 42th IEEE/ACM Int'l Symp. on Microarchitecture, 2009.