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Volumn 10, Issue 3, 2010, Pages 262-269

Design of a cascaded H-bridge multilevel inverter based on power electronics building blocks and control for high performance

Author keywords

Cascaded H bridge multilevel inverter; PEBB; PWM synchronization; Unbalance three phase control; Voltage delay compensation

Indexed keywords


EID: 77952638275     PISSN: 15982092     EISSN: None     Source Type: Journal    
DOI: 10.6113/JPE.2010.10.3.262     Document Type: Article
Times cited : (32)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.