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Volumn 102, Issue , 2010, Pages 287-299

A spice compatible model of on-wafer coupled interconnects for CMOS RFICs

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATION; CIRCUIT THEORY; CMOS INTEGRATED CIRCUITS; EQUIVALENT CIRCUITS; SCATTERING PARAMETERS; SPICE;

EID: 77952409735     PISSN: 10704698     EISSN: 15598985     Source Type: Journal    
DOI: 10.2528/PIER10010608     Document Type: Article
Times cited : (10)

References (15)
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    • Avinash, S., B. N. Joshi, and A. M. Mahajan, "Analysis of capacitance across interconnects of low-K dielectric used in a deep sub-micron CMOS technology," Progress In Electromagnetics Research Letters, Vol. 1, 189-196, 2008.
    • (2008) Progress In Electromagnetics Research Letters , vol.1 , pp. 189-196
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  • 3
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    • Study of loss effect of transmission lines and validity of a spice model in electromagnetic topology
    • Xie, H., J. Wang, R. Fan, and Y. Liu, "Study of loss effect of transmission lines and validity of a spice model in electromagnetic topology," Progress In Electromagnetics Research, PIER 90, 89-103,2009.
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    • Xie, H.1    Wang, J.2    Fan, R.3    Liu, Y.4
  • 4
    • 0035519748 scopus 로고    scopus 로고
    • Far-end crosstalk reduction in double-layered dielectric interconnects
    • Gazizov, T. R., "Far-end crosstalk reduction in double-layered dielectric interconnects," IEEE Trans. Electromagn. Compat., Vol. 43, No. 4, 566-572, 2001.
    • (2001) IEEE Trans. Electromagn. Compat , vol.43 , Issue.4 , pp. 566-572
    • Gazizov, T.R.1
  • 7
    • 0034269978 scopus 로고    scopus 로고
    • CAD-oriented equivalent circuit modeling of on-chip interconnects on lossy silicon substrate
    • Zheng, J., Y. Hahm, V. K. Tripathi, and A. Weisshaar, "CAD-oriented equivalent circuit modeling of on-chip interconnects on lossy silicon substrate," IEEE Trans. Microwave Theory Tech., Vol. 48, No. 9, 1443-1451, 2000.
    • (2000) IEEE Trans. Microwave Theory Tech , vol.48 , Issue.9 , pp. 1443-1451
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  • 8
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    • Characterization and modeling of multiple coupled on-chip interconnects on silicon substrate
    • Zheng, J., V. K. Tripathi, and A. Weisshaar, "Characterization and modeling of multiple coupled on-chip interconnects on silicon substrate," IEEE Trans. Microwave Theory Tech., Vol. 49, No. 10, 1733-1739, 2001.
    • (2001) IEEE Trans. Microwave Theory Tech , vol.49 , Issue.10 , pp. 1733-1739
    • Zheng, J.1    Tripathi, V.K.2    Weisshaar, A.3
  • 9
    • 33646466018 scopus 로고    scopus 로고
    • Modeling and analysis of crosstalk noise in coupled RLC interconnects
    • Agarwal, K., D. Sylvester, and D. Blaauw, "Modeling and analysis of crosstalk noise in coupled RLC interconnects," IEEE Trans. Computer-aided Design, Vol. 25, No. 5, 892-901, 2006.
    • (2006) IEEE Trans. Computer-aided Design , vol.25 , Issue.5 , pp. 892-901
    • Agarwal, K.1    Sylvester, D.2    Blaauw, D.3
  • 10
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    • SPICE compatible modelling of on-chip coupled interconnects
    • Kumar, R., K. Kang, S. C. R. Rustagi, K. Mouthaan, and T. K. S. Wong, "SPICE compatible modelling of on-chip coupled interconnects," Electron. Lett., Vol. 43, No. 9, 19-20, 2007.
    • (2007) Electron. Lett , vol.43 , Issue.9 , pp. 19-20
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  • 11
    • 27844448067 scopus 로고    scopus 로고
    • Equivalent circuit model of on-wafer CMOS interconnects for RFICs
    • Shi, X., J. Ma, K. S. Yeo, M. A. Do, and E. Li, "Equivalent circuit model of on-wafer CMOS interconnects for RFICs," IEEE Trans. VLSI Syst., Vol. 13, No. 9, 1060-1071, 2005.
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  • 12
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  • 13
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.