1D thickness scaling study of phase change material (Ge2Sb 2Te5) using a pseudo 3-terminal device

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2009, Pages

  Bae, Byoung Jae ^a   Kim, Sang Bum ^b   Zhang, Yuan ^b   Kim, Youngkuk ^a   Baek, In Gyu ^a   Park, Soonoh ^a   Yeo, In Seok ^a   Choi, Siyoung ^a   Moon, Joo Tae ^a   Philip Wong, H S ^b   Kim, Kinam ^a  

^a SAMSUNG Electronics   (South Korea)

^b Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELEVATED TEMPERATURE; READ OPERATION; TERMINAL DEVICES; THERMAL STABILITY; THICKNESS SCALING;

GERMANIUM; PHASE CHANGE MATERIALS; TELLURIUM COMPOUNDS; THERMOGRAVIMETRIC ANALYSIS;

ELECTRON DEVICES;

EID: 77952389720     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2009.5424412     Document Type: Conference Paper

References (7)

1. J.I. Lee, H. Park, S.L. Cho, Y.L. Park, B.J. Bae, J.H. Park, J.S. Park, H.G. An, J.S. Bae, D.H. Ahn, Y.T. Kim, H. Horii, S.A. Song, J.C. Shin, S.O. Park, H.S. Kim, U-In Chung, J.T. Moon, and B.I. Ryu, "Highly Scalable Phase Change Memory with CVD GeSbTe for Sub 50nm Generation," Symp. VLSI Tech Dig. pp. 102-103 (2008).
2. U. Russo, D. Ielmini, A. Redaelli, and A.L. Lacaita, "Modeling of Programming and Read Performance in Phase-Change Memories - Part I: Cell Optimization and Scaling," IEEE Trans. Electron Devices 55(2), pp. 506-514 (2008). (Pubitemid 351292038)
3. A.L. Lacaita, A. Redaelli, D. Ielmini, F. Pellizzer, A. Pirovano, A. Benvenuti, and R. Bez, "Electrothermal and phase-change dynamics in chalcogenide-based memories," IEDM Tech Dig. pp. 911-914 (2004).
4. D. Yu, S. Brittman, J.S. Lee, A.L. Falk, and H. Park, " Minimum Voltage for Threshold Switching in Nanoscale Phase-Change Memory," Nano Lett. 8(10), pp. 3429-3433 (2008).
5. D.-H. Kang, J.-H. Lee, J.H. Kong, D. Ha, J. Yu, C.Y. Um, J.H. Park, F. Yeung, J.H. Kim, W.I. Park, Y.J. Jeon, M.K. Lee, Y.J. Song, J.H. Oh, G.T. Jeong, and H.S. Jeong, "Two-bit cell operation in diode-switch phase change memory cells with 90nm technology," Symp. VLSI Tech Dig. pp. 98-99 (2008).
6. S. Braga, A. Cabrini, and G. Torelli, "Dependence of resistance drift on the amorphous cap size in phase change memory arrays," Appl. Phys. Lett. 94(9), 092112 (2009).
7. S. Raoux, J.L. Jordan-Sweet, and A.J. Kellock, "Crystallization properties of ultrathin phase change films," J. Appl. Phys. 103, 114310 (2008).