Hierarchical parallelization of an H.264/AVC video encoder

PARELEC 2006 - Proceedings: International Symposium on Parallel Computing in Electrical Engineering

Volumn , Issue , 2006, Pages 363-368

  Rodriguez A ^a   Gonzalez A ^a   Malumbres, M P ^b  

^a UNIVERSITAT POLITÈCNICA DE VALÈNCIA   (Spain)

^b MIGUEL HERNÁNDEZ UNIVERSITY   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

BIT RATES; COMPRESSION EFFICIENCY; COMPUTING DEMANDS; FRAME RATE; GENERAL PURPOSE; H.264 ENCODERS; H.264/AVC; H.264/AVC VIDEO; HIERARCHICAL PARALLELIZATION; LOW COSTS; LOW LATENCY; OFF-THE-SHELF COMPONENTS; PARALLEL PROCESSING; PARALLELIZATIONS; SPECIAL PURPOSE HARDWARE; VIDEO ENCODINGS; VIDEO QUALITY;

ELECTRICAL ENGINEERING; ENCODING (SYMBOLS); HARDWARE; IMAGE COMPRESSION; IMAGE RESOLUTION; MESSAGE PASSING; PARALLEL ARCHITECTURES;

MOTION PICTURE EXPERTS GROUP STANDARDS;

EID: 77952351951     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PARELEC.2006.42     Document Type: Conference Paper

References (12)

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