Understanding STI edge fringing field effect on the scaling of charge-trapping (CT) NAND flash and modeling of incremental step pulse programming (ISPP)

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2009, Pages

  Lue, Hang Ting ^a   Hsu, Tzu Hsuan ^a   Hsiao, Yi Hsuan ^a   Lai, Sheng Chih ^a   Lai, Erh Kun ^a   Hong, Shih Ping ^b   Wu, Ming Tsung ^b   Hsu, F H ^b   Lien, N Z ^b   Lu, Chi Pin ^b   Wang, Szu Yu ^b   Hsieh, Jung Yu ^b   Yang, Ling Wu ^b   Yang, Tahone ^b   Chen, Kuang Chao ^b   Hsieh, Kuang Yeu ^a   Liu, Rich ^a   Lu, Chih Yuan ^a  

^a MACRONIX INTERNATIONAL CO LTD   (Taiwan)

^b Technology Development Center   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

3D SIMULATIONS; BODY TIED; DISTURB WINDOW; FIELD ENHANCEMENT FACTOR; FRINGING FIELD EFFECTS; FRINGING FIELDS; GATE-ALL-AROUND DEVICES; IDEAL VALUES; MEMORY WINDOW; NAND FLASH; PARASITIC LEAKAGES; SELF-ALIGNED; STEP PULSE; STI STRUCTURES; SUB-THRESHOLD CURRENT; TUNNEL OXIDE]; TUNNELING ,;

ELECTRIC FIELDS; ELECTRON DEVICES; ELECTRONS; THREE DIMENSIONAL COMPUTER GRAPHICS;

THREE DIMENSIONAL;

EID: 77952331618     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2009.5424209     Document Type: Conference Paper

References (5)

1. H. T. Lue et al, IEDM Tech. Dig., 2007, pp. 161-164.
2. H. T. Lue et al, VLSI Symposia, 2008, pp. 116-117.
3. K.D. Suh, et, al, IEEE Journal of Solid-State Circuits, pp. 1149-1156, 1995.
4. H. T. Lue et al, IRPS 2008, pp. 693-694.
5. H. T. Lue et al, IEEE T-ED 2008, pp. 2218-2228.