Cortical architectures on a GPGPU

International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

Volumn , Issue , 2010, Pages 12-18

  Nere, Andrew ^a   Lipasti, Mikko ^a  

^a University of Wisconsin Madison   (United States)

Author keywords

Cortical architecture; CUDA; GPGPU; Hypercolumn; Minicolumn

Indexed keywords

BASIC BUILDING BLOCK; COMPUTATIONAL ABILITY; COMPUTING DEVICES; CORTICAL ARCHITECTURE; CURRENT TRENDS; ENERGY EFFICIENT; FAULT-TOLERANT; FAULTY DEVICES; HUMAN BRAIN; INITIAL DESIGN; INTELLIGENT MODELS; MAMMALIAN BRAIN; MULTIPLE KERNELS; PARALLEL COMPUTING; POWER CONSUMPTION; TRAINING PHASE;

MAMMALS; NEUROPHYSIOLOGY; PARALLEL ARCHITECTURES;

PROGRAM PROCESSORS;

EID: 77952252986     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1735688.1735693     Document Type: Conference Paper

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