3.3GHz DCO with a frequency resolution of 150Hz for all-digital PLL

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 48-49

  Fanori, Luca ^a   Liscidini, Antonio ^a   Castello, Rinaldo ^a  

^a UNIVERSITY OF PAVIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALL DIGITAL PHASE LOCKED LOOP; ALL-DIGITAL PLL; CAPACITOR BANK; COARSE TUNING; DATA CONVERTER; DIGITAL TUNING; DIGITALLY CONTROLLED OSCILLATORS; DISCRETIZATIONS; EMISSION MASK; FINE TUNING; FREQUENCY CONTROL; FREQUENCY RESOLUTIONS; HIGHER FREQUENCIES; LC-OSCILLATORS; OUT-OF-BAND; PARASITICS; QUANTIZATION NOISE; TEMPERATURE VARIATION;

CAPACITANCE; CAPACITORS; OSCILLATORS (ELECTRONIC); TUNING;

PHASE LOCKED LOOPS;

EID: 77952174632     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5434057     Document Type: Conference Paper

References (3)

1. R. Staszewski et al., "A Digitally Controlled Oscillator in a 90nm Digital CMOS Process for Mobile Phones," IEEE J. Solid-State Circuits, vol. 40, no. 11, pp. 2203-2211, 2005.
2. Y. Chen et al.,"A 9GHz Dual-Mode Digitally Controlled Oscillator for GSM/UMTS Transceivers in 65nm CMOS," IEEE Asian Solid-State Circuits Conference ( ASSCC '07), pp. 432-435, 2007.
3. A. Mazzanti and P. Andreani, "Class-C Harmonic CMOS VCOs, With a General Result on Phase Noise," IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2716-2729, 2008.