Acceleration of conjugate gradient method for circuit simulation using CUDA

16th International Conference on High Performance Computing, HiPC 2009 - Proceedings

Volumn , Issue , 2009, Pages 438-444

  Maringanti, Anirudh ^a   Athavale, Viraj ^a   Patkar, Sachin B ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATORS; CONJUGATE GRADIENT; CURRENT GENERATION; CURRENT SOURCES; GRAPHICS CARD; LARGE CIRCUITS; MEMORY BANDWIDTHS; PROCESSING POWER; SINGLE-THREADED; SYSTEM OF LINEAR EQUATIONS;

CIRCUIT SIMULATION;

CONJUGATE GRADIENT METHOD;

EID: 77952167599     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HIPC.2009.5433184     Document Type: Conference Paper

References (13)

1. NVIDIA GeForce GTX 200 GPU Architectural Overview, NVIDIA, May 2008.
2. G. Trivedi, M. P. Desai, and H. Narayanan, "Fast dc analysis and its application to combinatorial optimization problems," in Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design, 2006, pp. 695-700. (Pubitemid 44362667)
3. J. R. Shewchuck, "An introduction to the conjugate gradient method without the agonizing pain," Carnegie Mellon University, Tech. Rep., August 1994.
4. J. Bolz, I. Farmer, E. Grinspun, and P. Schröoder, "Sparse matrix solvers on the GPU: Conjugate gradients and multigrid," in SIGGRAPH '03: ACM SIGGRAPH 2003 Papers, 2003, pp. 917-924.
5. D. Göddeke, R. Strzodka, and S. Turek, "Performance and accuracy of hardware-oriented native-, emulated-and mixed-precision solvers in FEM simulations," Int. J. Parallel Emerg. Distrib. Syst., vol. 22, no. 4, pp. 221-256, 2007.
6. S. Sengupta, M. Harris, Y. Zhang, and J. D. Owens, "Scan primitives for GPU computing," in Proceedings of the 22nd ACM SIGGRAPH/ EUROGRAPHICS Symposium on Graphics hardware, 2007, pp. 97-106.
7. L. Buatois, G. Caumon, and B. Lvy, "Concurrent number cruncher: An efficient sparse linear solver on the GPU," in High Performance Computation Conference (HPCC), Springer Lecture Notes in Computer Sciences, 2007.
8. S. Williams, L. Oliker, R. Vuduc, J. Shalf, K. Yelick, and J. Demmel, "Optimization of sparse matrix-vector multiplication on emerging multicore platforms," in Proceedings of the 2007 ACM/IEEE conference on Supercomputing, 2007, pp. 1-12.
9. N. Bell and M. Garland, "Efficient sparse matrix-vector multiplication on CUDA," NVIDIA, Tech. Rep., December 2008.
10. N. Bell and M. Garland, "Implementing sparse matrix-vector multiplication on throughput-oriented processors," in SC '09: Proceedings of the 2009 ACM/IEEE conference on Supercomputing, in press.
11. NVIDIA CUDA Programming Guide 2.0, NVIDIA, June 2008.
12. V. Volkov and J. W. Demmel, "Benchmarking GPUs to tune dense linear algebra," in Proceedings of the 2008 ACM/IEEE conference on Supercomputing, 2008, pp. 1-11.
13. B. Schiffher, J. Li, and L. Behjat, "A multilevel eigenvalue based circuit partitioning technique," in 5th International Workshop on Silicon-On-Chip for Real-Time Applications, July 2005.